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公开(公告)号：US20050146952A1
公开(公告)日：2005-07-07
申请号：US10745294
申请日：2003-12-23
CPC分类号： G11C29/848 , G11C29/808
摘要： An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.
摘要翻译： 一种集成电路存储器，包括至少两个存储体，每个存储体具有存储元件的阵列，所述存储元件阵列具有至少一个冗余列，并且每个与特定读出放大器相关联，每行与存储体共用的输入/输出缓冲器电路行以及每个存储体 ，用于将冗余列分配给连接到所述缓冲器之一的输入/输出线的电路。 对于当前秩的行，可以针对前一列的列和朝向下一列的列执行分配。
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公开(公告)号：US20050157534A1
公开(公告)日：2005-07-21
申请号：US10627955
申请日：2003-07-25
申请人： Richard Ferrant , Francois Jacquet
发明人： Richard Ferrant , Francois Jacquet
IPC分类号： G11C11/406 , G11C11/24
CPC分类号： G11C11/406
摘要： A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.
摘要翻译： 一种DRAM，包括排列成行和列的存储元件的阵列，并且用于每列：写入装置，其适于将至少一个所选元素偏置到从第一预定高电平和第二预定低电平中选择的电荷电平 与读取电路组合，适于确定所存储的电荷电平是否大于或小于预定电荷电平; 以及隔离电路，其适于将阵列与读取和/或写入装置隔离，每列还包括与读取和写入电路不同的刷新装置，用于在第一和第二预定级别之外增加存储在存储元件中的电荷 。
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公开(公告)号：US06316986B1
公开(公告)日：2001-11-13
申请号：US09578780
申请日：2000-05-25
申请人： Richard Ferrant , Francois Jacquet
发明人： Richard Ferrant , Francois Jacquet
IPC分类号： G05F110
CPC分类号： H02M3/07
摘要： At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.
摘要翻译： 在充电阶段，通过与电容器（PC）的第一端子（T1）串联连接的两个互补充电晶体管（TR1，TR2）对电容器（PC）进行充电。 在电压倍增阶段，将输入电压（Vdd）输送到电容器的第二端子（T2），并且相对于输入电压增加的输出电压（Vout）在第一端子（T1）处被恢复 电容器和电容器在放电阶段被放电。 在三相期间，直接连接到电容器的第一端子（T1）的充电晶体管（TR2）的基板（BK2）被从属于同一充电晶体管（TR2）的源极（S2），同时仍然保持源极 基极结和该充电晶体管（TR2）的漏 - 基极结反向偏置。
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4.发明授权公开(公告)号：US07751229B2
公开(公告)日：2010-07-06
申请号：US11617336
申请日：2006-12-28
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.
摘要翻译： 提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。 该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。 该装置还包括在立柱中的最大限制单元的反射镜中的仿真装置，用于改变反射镜列的反射镜电源电压（VDDMMOCK）的装置，以及用于将模拟的反射镜电源电压复制的装置 基列。
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公开(公告)号：US20090196085A1
公开(公告)日：2009-08-06
申请号：US12421821
申请日：2009-04-10
申请人： Philippe Roche , Francois Jacquet
发明人： Philippe Roche , Francois Jacquet
CPC分类号： G11C11/4125 , G11C5/005
摘要： A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.
摘要翻译： 存储器单元被保护以防止电流或电压尖峰。 小区包括用于在至少一对互补节点中存储信息的一组冗余数据存储节点。 小区还包括用于在当前或电压尖峰之后将信息恢复到其初始状态的电路，其使用存储在另一节点中的信息来修改对中的一个节点中的信息。 单元中每对的数据存储节点在限定存储单元的边界的衬底的区域内相互注入相对导电类型的相对侧。
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公开(公告)号：US20080198679A1
公开(公告)日：2008-08-21
申请号：US12030463
申请日：2008-02-13
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C11/412 , G11C11/413
摘要： A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can comprise a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.
摘要翻译： 电路包括具有高电压供应节点和低电压供应节点的存储单元。 功率复用电路被提供用于根据小区的当前操作模式选择性地将第一组电压和第二组电压中的一个应用于小区的高电压和低电压供应节点。 如果单元处于活动读或写模式，则多路复用电路选择性地将第一组电压施加到高电压和低电压供应节点。 相反，如果单元处于待机无读或不写模式，则多路复用电路选择性地将第二组电压施加到高电压和低电压供应节点。 第二组电压偏离第一组电压。 更具体地，第二组电压中的低电压高于第一组电压中的低电压，并且其中第二组电压中的高电压小于第一组电压中的高电压。 单元可以是单元阵列的成员，在这种情况下，根据阵列的主动/待机模式，选择性地施加电压应用于阵列。 阵列可以包括包括许多块或部分的整个存储器装置内的块或部分，在这种情况下，根据块/部分本身的主动/待机模式，选择性地施加电压施加到各个块/部分。
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7.发明申请PROGRAMMABLE SRAM SOURCE BIAS SCHEME FOR USE WITH SWITCHABLE SRAM POWER SUPPLY SETS OF VOLTAGES 有权可编程SRAM SRAM源开发方案可供选择的SRAM供电电压组公开(公告)号：US20080198678A1
公开(公告)日：2008-08-21
申请号：US12029366
申请日：2008-02-11
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147 , G11C5/148 , G11C11/41 , G11C11/413 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.
摘要翻译： 存储电路具有高电压和低电压电源节点。 根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。 如果处于主动读/写模式，则选择性地施加第一组电压。 相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。 所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压 所述第一组电压通过多个高偏移电压中的所选择的一个。 偏移电压由选择性有效的基于二极管的电路提供。 选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。
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8.发明申请公开(公告)号：US20080159014A1
公开(公告)日：2008-07-03
申请号：US11617336
申请日：2006-12-28
申请人： Cyrille Dray , Francois Jacquet
发明人： Cyrille Dray , Francois Jacquet
IPC分类号： G11C5/14
CPC分类号： G11C11/413
摘要： The invention relates to a device, and also to a corresponding method of implementation, for SRAM memory information storage, powered by a voltage VDD and comprising: an array of base cells organised in base columns, and at least one mirror column of mirror cells, liable to simulate the behaviour of the cells in a base column, The invention is characterised in that the device further comprises: Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying the mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.
摘要翻译： 本发明涉及一种由电压VDD供电的SRAM存储器信息存储器的器件以及相应的实现方法，包括：组合在基本列中的基本单元阵列，以及镜像单元的至少一个反射镜列， 本发明的特征在于，该装置还包括：在反射镜列中的仿真装置，其是基极柱中最大限制电池的装置，用于改变反射镜电源电压的装置 （VDDMMOCK），以及用于复制仿真基列中的反射镜电源电压的装置。
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公开(公告)号：US20080144413A1
公开(公告)日：2008-06-19
申请号：US11951001
申请日：2007-12-05
IPC分类号： G11C7/12
CPC分类号： G11C11/419
摘要： A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.
摘要翻译： SRAM类型的存储器件具有由以行和列组织的基本存储器单元构成的存储器计划。 列的每个单元连接在读取操作期间预充电的两个位线之间。 电路被提供用于产生位线的预充电电压，其小于设备的额定电源电压。
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10.发明授权公开(公告)号：US07109541B2
公开(公告)日：2006-09-19
申请号：US10318955
申请日：2002-12-13
IPC分类号： H01L21/70
CPC分类号： H03K3/0375 , G11C11/4125 , H01L27/1104
摘要： A component of an integrated circuit comprises a first capacitor and a second capacitor series-connected between a first node and a second node of the component. This has application to logic circuits and bistable circuits, for example, SRAM type memories, flip-flop trigger circuits, etc.
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