公开(公告)号：US20080317244A1

公开(公告)日：2008-12-25

申请号：US12200792

申请日：2008-08-28

申请人： Leonard D. Rarick ,  Christopher H. Olson

发明人： Leonard D. Rarick ,  Christopher H. Olson

IPC分类号： H04L9/06

CPC分类号： H04L9/0625 ,  H04L2209/12

摘要： An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output. The first exclusive-or operator is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output. The second exclusive-or operator is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output. The third exclusive-or operator is configured to receive the Left Half input and the data output by the first group of transistors.

摘要翻译： 适于执行数据加密标准的至少一部分的执行单元。 执行单元包括左半输入; 一键输入 和一个表输入。 执行单元还包括被配置为接收表输入，执行表查找和输出数据的第一组晶体管。 执行单元还包括具有两个输入和一个输出的第一个异或运算符。 第一个独占或运算符被配置为接收左半输入和键输入。 执行单元还包括具有两个输入和一个输出的第二个异或运算符。 第二异或运算符被配置为接收由第一组晶体管输出的数据并且接收第一异或运算符的输出。 执行单元还包括具有两个输入和一个输出的第三个异或运算符。 第三个异或运算符被配置为接收第一组晶体管的左半输入和数据输出。

公开(公告)号：US08433742B2

公开(公告)日：2013-04-30

申请号：US12187286

申请日：2008-08-06

申请人： Leonard D. Rarick

发明人： Leonard D. Rarick

IPC分类号： G06F11/10 ,  G06F7/38

CPC分类号： G06F11/1405 ,  G06F11/104 ,  H03M13/158

摘要： During a method, a modulus circuit determines a modulus base p of a first number and a modulus base p of a second number. Also, the modulus circuit performs the operation using the modulus base p of the first number and the modulus base p of the second number, and calculates a modulus base p of the result of the operation involving the first number and the second number. Next, the modulus circuit compares the result of the operation carried out on the modulus base p of the first number and the modulus base p of the second number with the modulus base p of the operation performed on the first number and the second number to identify potential errors associated with the operation. Moreover, the modulus circuit repeats the method to identify additional potential errors associated with the operation, where the determining and calculating operations are repeated using moduli base q.

摘要翻译： 在一种方法中，模数电路确定第一数量的模数基数p和第二数目的模数基数p。 此外，模数电路使用第一数量的模量基数p和第二数量的模量基数p进行操作，并且计算涉及第一数量和第二数量的操作结果的模数基数p。 接下来，模数电路将对第一数量的模量基数p和第二数量的模量基数p进行的操作的结果与在第一数字和第二数目上执行的操作的模数基数p进行比较，以识别 与操作相关的潜在错误。 此外，模数电路重复该方法以识别与操作相关联的附加潜在误差，其中使用模量基准q重复确定和计算操作。

公开(公告)号：US20120041997A1

公开(公告)日：2012-02-16

申请号：US13280180

申请日：2011-10-24

申请人： Murali K. Inaganti ,  Leonard D. Rarick

发明人： Murali K. Inaganti ,  Leonard D. Rarick

IPC分类号： G06F7/499

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F9/30014

摘要： A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.

摘要翻译： 包括单个未融合融合的浮点乘法（FMA）模块的计算机处理器计算用于融合乘法加法运算和未加密乘法加法运算的浮点数的操作A * B + C的结果。 在一个实施例中，利用额外的硬件来增加融合乘法加法实现，其中计算未加密的乘法加法结果，而不增加额外的流水线级。 在一个实施例中，使用单个操作码来启动由融合未分配的浮点乘法（FMA）模块进行的计算，该操作码确定是否生成融合乘法加法结果或未合并的乘法加法结果。

公开(公告)号：US07599982B1

公开(公告)日：2009-10-06

申请号：US11223837

申请日：2005-09-08

申请人： Leonard D. Rarick

发明人： Leonard D. Rarick

IPC分类号： G06F7/52

CPC分类号： G06F7/535 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F2207/5356

摘要： One embodiment of the present invention provides a system that uses the Newton-Raphson technique to perform a division operation. During operation, the system receives a numerator a and a denominator b. The system then divides a by b by first using the Newton-Raphson technique to calculate 1/b, and then multiplying 1/b by a to produce the result a/b. While using Newton-Raphson technique to find 1/b, the system first obtains an initial estimate x0 for 1/b and then iteratively solves the equation xi+1=xi(2−bxi). Each iteration involves: (1) using a multiplier circuit to multiply b by xi to compute bxi; (2) performing a bit-wise complement operation on bxi to compute 2−bxi, whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation. (3) The system then uses the multiplier circuit to multiply xi by 2−bxi to compute xi(2−bxi).

摘要翻译： 本发明的一个实施例提供一种使用牛顿 - 拉夫逊（Newton-Raphson）技术进行分割操作的系统。 在运行期间，系统接收分子a和分母b。 系统然后首先使用牛顿 - 拉夫逊（Newton-Raphson）技术来划分乘以b，计算1 / b，然后乘以1 / b乘以a产生结果a / b。 当使用Newton-Raphson技术找到1 / b时，系统首先获得1 / b的初始估计x0，然后迭代地求解方程xi + 1 = xi（2-bxi）。 每次迭代涉及：（1）使用乘法器电路将b乘以xi来计算bxi; （2）对bxi进行逐位补码运算以计算2-bxi，从而不需要通过加法器电路或乘法/加法电路的附加通过执行减法运算。 （3）系统然后使用乘法器电路将xi乘以2-bxi来计算xi（2-bxi）。

公开(公告)号：US07373368B1

公开(公告)日：2008-05-13

申请号：US10891978

申请日：2004-07-15

申请人： Leonard D. Rarick ,  Shu-Chin Tai

发明人： Leonard D. Rarick ,  Shu-Chin Tai

IPC分类号： G06F7/52

CPC分类号： G06F7/724 ,  G06F7/533

摘要： A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The summing circuit includes a plurality of rows. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a plurality of compressors in the first row of the summing circuit. The plurality of compressors each has more than three inputs that receive data, a carry output, and a sum output.

摘要翻译： 乘法执行单元，其可以生成被乘数和乘数的整数乘积，并且还可操作以产生被乘数和乘数的XOR乘积。 乘法执行单元包括用于求和多个部分乘积的求和电路。 求和电路包括多行。 求和电路可以生成多个部分乘积的整数，并且可以产生多个部分乘积的XOR和。 求和电路包括在求和电路的第一行中的多个压缩机。 多个压缩机每个具有多于三个接收数据的输入，进位输出和和输出。

公开(公告)号：US08046399B1

公开(公告)日：2011-10-25

申请号：US12020486

申请日：2008-01-25

申请人： Murali K. Inaganti ,  Leonard D. Rarick

发明人： Murali K. Inaganti ,  Leonard D. Rarick

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F9/30014

摘要： A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.

摘要翻译： 包括单个未融合融合的浮点乘法（FMA）模块的计算机处理器计算用于融合乘法加法运算和未加密乘法加法运算的浮点数的操作A * B + C的结果。 在一个实施例中，利用额外的硬件来增加融合乘法加法实现，其中计算未加密的乘法加法结果，而不增加额外的流水线级。 在一个实施例中，使用单个操作码来启动由融合未分配的浮点乘法（FMA）模块进行的计算，该操作码确定是否生成融合乘法加法结果或未合并的乘法加法结果。

公开(公告)号：US20100057824A1

公开(公告)日：2010-03-04

申请号：US12203644

申请日：2008-09-03

申请人： Leonard D. Rarick

发明人： Leonard D. Rarick

IPC分类号： G06F7/38 ,  G06F7/52

CPC分类号： G06F7/5338

摘要： A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central processing unit. The central processing unit includes a carry save adder configured to add a plurality of partial products obtained from the product of the first term and the second term to obtain a first partial result and a second partial result, a multiplexer configured to output one selected from the group consisting of the second term, the third term, and zero, and an alignment shifter configured to shift an output of the multiplexer to align the output of the multiplexer with the first partial result and the second partial result to obtain a shifted term. The shifted term, the first partial result and the second partial result are added together to obtain a result of the binary operation.

摘要翻译： 一种用于计算二进制运算的计算机系统，所述二进制运算涉及第一项乘以产生产品的第二项，其中所述乘积有条件地添加到中央处理单元中的第三项。 中央处理单元包括进位保存加法器，其被配置为添加从第一项和第二项的乘积获得的多个部分乘积以获得第一部分结果和第二部分结果;多路复用器，被配置为输出从 由第二项，第三项和第零组成的组，以及对准移位器，被配置为移位多路复用器的输出以使多路复用器的输出与第一部分结果和第二部分结果对齐以获得偏移项。 将移位的项，第一部分结果和第二部分结果相加在一起以获得二进制操作的结果。

公开(公告)号：US20100036901A1

公开(公告)日：2010-02-11

申请号：US12187286

申请日：2008-08-06

申请人： Leonard D. Rarick

发明人： Leonard D. Rarick

IPC分类号： G06F11/07

CPC分类号： G06F11/1405 ,  G06F11/104 ,  H03M13/158

摘要： During a method, a modulus circuit determines a modulus base p of a first number and a modulus base p of a second number. Also, the modulus circuit performs the operation using the modulus base p of the first number and the modulus base p of the second number, and calculates a modulus base p of the result of the operation involving the first number and the second number. Next, the modulus circuit compares the result of the operation carried out on the modulus base p of the first number and the modulus base p of the second number with the modulus base p of the operation performed on the first number and the second number to identify potential errors associated with the operation. Moreover, the modulus circuit repeats the method to identify additional potential errors associated with the operation, where the determining and calculating operations are repeated using moduli base q.

摘要翻译： 在一种方法中，模数电路确定第一数量的模数基数p和第二数目的模数基数p。 此外，模数电路使用第一数量的模量基数p和第二数量的模量基数p进行操作，并且计算涉及第一数量和第二数量的操作结果的模数基数p。 接下来，模数电路将对第一数量的模量基数p和第二数量的模量基数p进行的操作的结果与在第一数字和第二数目上执行的操作的模数基数p进行比较，以识别 与操作相关的潜在错误。 此外，模数电路重复该方法以识别与操作相关联的附加潜在误差，其中使用模量基准q重复确定和计算操作。

公开(公告)号：US07599980B1

公开(公告)日：2009-10-06

申请号：US11223836

申请日：2005-09-08

申请人： Leonard D. Rarick

发明人： Leonard D. Rarick

IPC分类号： G06F7/38

CPC分类号： G06F7/5525

摘要： One embodiment of the present invention provides a system that uses the Newton-Raphson technique to compute a square-root. During operation, the system receives a radicand b. Next, the system calculates the square root of b, √{square root over (b)}, by first using the Newton-Raphson technique to find 1/√{square root over (b)}, and then multiplying 1/√{square root over (b)} by b to produce √{square root over (b)}. While using the Newton-Raphson technique to find 1/√{square root over (b)}, the system first obtains an initial estimate x0 for 1/√{square root over (b)} and then iteratively solves the equation x i + 1 = x i ⁢ ⁢ ( 3 - bx i 2 2 ) . Each iteration involves: (1) using a multiplier circuit twice to compute bxi2; (2) performing a bit-wise complement operation on bxi2, shifting the result, and modifying the first two bits of the result to compute 3 - bx i 2 2 , whereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation; and finally (3) using the multiplier circuit to multiply xi by 3 - bx i 2 2 to compute x i ⁢ ⁢ ( 3 - bx i 2 2 ) .

公开(公告)号：US06768684B2

公开(公告)日：2004-07-27

申请号：US10057172

申请日：2002-01-25

申请人： Leonard D. Rarick

发明人： Leonard D. Rarick

IPC分类号： G11C700

CPC分类号： G11C17/18

摘要： A system and method is provided for minimizing read-only data retrieval time and/or area through the use of combinatorial logic. In one embodiment of the present invention, two address bits are provided to a binary logic function device. The binary logic function device uses the two address bits and predetermined logic functions (i.e., functions that represent a plurality of read-only data values) to produce a binary value—which is the requested read-only data. In another embodiment, the binary values produced by the binary logic function device are provided to at least one multiplexer. The at least one multiplexer uses at least a portion of the remaining bits (i.e., the address bits not being provided to the binary logic function device) to select (or narrow down) which binary values may be the read-only data requested. If the output of the at least one multiplexer contains more than one binary value, then those values are provided to at least one other multiplexer. The at least one other multiplexer uses the remainder of the remaining bits to select which binary value is the read-only data requested.

摘要翻译： 提供了一种通过使用组合逻辑来最小化只读数据检索时间和/或区域的系统和方法。 在本发明的一个实施例中，两个地址位被提供给二进制逻辑功能器件。 二进制逻辑功能器件使用两个地址位和预定的逻辑功能（即，表示多个只读数据值的功能）来产生二进制值，其是所请求的只读数据。 在另一个实施例中，由二进制逻辑功能器件产生的二进制值提供给至少一个多路复用器。 所述至少一个多路复用器使用剩余位的至少一部分（即，未提供给二进制逻辑功能器件的地址位）来选择（或缩小）哪些二进制值可以是所请求的只读数据。 如果至少一个多路复用器的输出包含多于一个二进制值，则将这些值提供给至少一个其他多路复用器。 至少另一个多路复用器使用其余位的余数来选择哪个二进制值是所请求的只读数据。