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1.发明申请FUSED MULTIPLY-ADD ROUNDING AND UNFUSED MULTIPLY-ADD ROUNDING IN A SINGLE MULTIPLY-ADD MODULE 有权多功能多路复用器中的多路复用和多路复用多路复用公开(公告)号：US20120041997A1
公开(公告)日：2012-02-16
申请号：US13280180
申请日：2011-10-24
IPC分类号： G06F7/499
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014
摘要： A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.
摘要翻译： 包括单个未融合融合的浮点乘法（FMA）模块的计算机处理器计算用于融合乘法加法运算和未加密乘法加法运算的浮点数的操作A * B + C的结果。 在一个实施例中，利用额外的硬件来增加融合乘法加法实现，其中计算未加密的乘法加法结果，而不增加额外的流水线级。 在一个实施例中，使用单个操作码来启动由融合未分配的浮点乘法（FMA）模块进行的计算，该操作码确定是否生成融合乘法加法结果或未合并的乘法加法结果。
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2.发明授权Fused multiply-add rounding and unfused multiply-add rounding in a single multiply-add module 有权在单个乘法模块中融合乘法加法和未加法乘法加法舍入公开(公告)号：US08990283B2
公开(公告)日：2015-03-24
申请号：US13280180
申请日：2011-10-24
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014
摘要： A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.
摘要翻译： 包括单个未融合融合的浮点乘法（FMA）模块的计算机处理器计算用于融合乘法加法运算和未加密乘法加法运算的浮点数的操作A * B + C的结果。 在一个实施例中，利用额外的硬件来增加融合乘法加法实现，其中计算未加密的乘法加法结果，而不增加额外的流水线级。 在一个实施例中，使用单个操作码来启动由融合未分配的浮点乘法（FMA）模块进行的计算，该操作码确定是否生成融合乘法加法结果或未合并的乘法加法结果。
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3.发明授权Fused multiply-add rounding and unfused multiply-add rounding in a single multiply-add module 有权在单个乘法模块中融合乘法加法和未加法乘法加法舍入公开(公告)号：US08046399B1
公开(公告)日：2011-10-25
申请号：US12020486
申请日：2008-01-25
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014
摘要： A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.
摘要翻译： 包括单个未融合融合的浮点乘法（FMA）模块的计算机处理器计算用于融合乘法加法运算和未加密乘法加法运算的浮点数的操作A * B + C的结果。 在一个实施例中，利用额外的硬件来增加融合乘法加法实现，其中计算未加密的乘法加法结果，而不增加额外的流水线级。 在一个实施例中，使用单个操作码来启动由融合未分配的浮点乘法（FMA）模块进行的计算，该操作码确定是否生成融合乘法加法结果或未合并的乘法加法结果。
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公开(公告)号：US07934080B2
公开(公告)日：2011-04-26
申请号：US12128332
申请日：2008-05-28
申请人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
发明人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
IPC分类号： G06F9/312
CPC分类号： G06F9/3842 , G06F9/3834 , G06F9/3863
摘要： Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.
摘要翻译： 本发明的实施例提供了一种处理器，其将存储结合在N入口先进先出（FIFO）存储队列中。 在这些实施例中，处理器通过在生成检查点之前执行指令来开始。 在生成检查点之前执行指令时，处理器被配置为对存储队列中的现有条目执行有限或不合并存储。 然后，在检测到预定条件时，处理器被配置为产生检查点。 生成检查点后，处理器配置为继续执行指令。 在检查点生成后执行指令时，处理器被配置为将后续存储自由合并到存储队列中的后检查点条目中。
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公开(公告)号：US20090300338A1
公开(公告)日：2009-12-03
申请号：US12128332
申请日：2008-05-28
申请人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
发明人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3834 , G06F9/3863
摘要： Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.
摘要翻译： 本发明的实施例提供了一种处理器，其将存储结合在N入口先进先出（FIFO）存储队列中。 在这些实施例中，处理器通过在生成检查点之前执行指令来开始。 在生成检查点之前执行指令时，处理器被配置为对存储队列中的现有条目执行有限或不合并存储。 然后，在检测到预定条件时，处理器被配置为生成检查点。 生成检查点后，处理器配置为继续执行指令。 在检查点生成后执行指令时，处理器被配置为将后续存储自由合并到存储队列中的后检查点条目中。
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