公开(公告)号：US08103986B2

公开(公告)日：2012-01-24

申请号：US12276263

申请日：2008-11-21

Applicant: Louis Scheffer

Inventor： Louis Scheffer

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/10

Abstract: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.

公开(公告)号：US07302672B2

公开(公告)日：2007-11-27

申请号：US11143361

申请日：2005-06-01

Applicant: Robert C. Pack ,  Louis Scheffer

Inventor： Robert C. Pack ,  Louis Scheffer

IPC: G06F17/50

CPC classification number: G03F1/68 ,  G03F1/36 ,  G03F1/78

Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

Abstract translation: 一种用于产生光刻掩模的方法包括产生集成电路设计数据和使用来自集成电路设计数据的上下文信息来写入掩模。

公开(公告)号：US20060265679A1

公开(公告)日：2006-11-23

申请号：US11419495

申请日：2006-05-20

Applicant: Louis Scheffer ,  Akira Fujimura

Inventor： Louis Scheffer ,  Akira Fujimura

IPC: G06F17/50 ,  G06F19/00

CPC classification number: G06F17/5068 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/70425 ,  G05B2219/35028 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.

Abstract translation: 本发明的一些实施例提供了一种用于设计集成电路（“IC”）布局的制造感知过程。 该过程接收制造配置，其指定用于基于IC布局来制造IC的一组机器的一组制造设置。 该过程基于指定的制造配置定义一组设计规则。 该过程使用一组设计规则来设计IC布局。 本发明的一些实施例提供了用于制造集成电路（“IC”）的设计感知过程。 该过程接收具有相关联的一组设计属性的IC设计。 该过程指定制造配置，其指定用于制造IC的一组机器的一组制造设置，其中指定的一组制造设置基于该组设计属性。 该过程基于制造设置制造IC。

公开(公告)号：US20050015739A1

公开(公告)日：2005-01-20

申请号：US10621114

申请日：2003-07-14

Applicant: Louis Scheffer ,  Kenji Yoshida ,  Yoshikuni Abe ,  Aki Fujimura ,  Robert Pack

Inventor： Louis Scheffer ,  Kenji Yoshida ,  Yoshikuni Abe ,  Aki Fujimura ,  Robert Pack

IPC: G03F7/20 ,  G06F9/45 ,  G06F9/455 ,  G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5068 ,  G03F1/68

Abstract: To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.

Abstract translation: 为了增加掩码的写入速度，可以使用上下文信息来区分与属性关联的掩码部分的属性以及不太关键的部分。 通过使用可以从特征的设计上下文导出的信息，可以以更高的速度写入掩码，而不会牺牲重要属性或特征的准确性。