公开(公告)号：US09136006B2

公开(公告)日：2015-09-15

申请号：US13946123

申请日：2013-07-19

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Ji-Yu Hung

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/28

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/28

Abstract: A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level VPRE. The method includes enabling current flow through selected memory cells on the plurality of bit lines to a reference line or to reference lines coupled to a reference voltage. The method includes preventing a voltage change as a result of the current flow on the bit lines from causing a bit line voltage to pass outside a range between the first level and a second level VKEEP, where the second level is lower than the first level and higher than the reference voltage. The method includes sensing data in the selected memory cells.

Abstract translation: 提供了一种用于感测存储器件中的数据的方法。 存储器件包括耦合到多个位线的存储器单元块。 该方法包括将多个位线预充电到第一级VPRE。 该方法包括实现电流流过多条位线上的选定存储单元到参考线或耦合到参考电压的参考线。 该方法包括防止由于位线上的电流而导致的电压变化导致位线电压超出第一电平和第二电平VKEEP之间的范围，其中第二电平低于第一电平， 高于参考电压。 该方法包括感测所选存储单元中的数据。

公开(公告)号：US20240233783A1

公开(公告)日：2024-07-11

申请号：US18150584

申请日：2023-01-05

Applicant: Macronix International Co., Ltd.

Inventor： Ji-Yu Hung ,  E-Yuan Chang

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1084 ,  G11C7/1087

Abstract: Systems, methods, circuits, and apparatus for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, a page buffer circuit including a plurality of page buffers, and a cache data latch (CDL) circuit including a plurality of caches coupled to the plurality of page buffers through a plurality of data bus sections. The plurality of data bus sections are configured to be conductively connected together as a data bus for data transfer. Each data bus section corresponds to a page buffer in the page buffer circuit and is configured to conductively separate from at least one adjacent data bus section for data sensing in the memory cell array.

公开(公告)号：US09153328B2

公开(公告)日：2015-10-06

申请号：US14319457

申请日：2014-06-30

Applicant: Macronix International Co., Ltd.

Inventor： Ji-Yu Hung

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

Abstract: A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.

Abstract translation: 页缓冲电路耦合到存储器阵列的位线。 页面缓冲电路包括在多阶段程序操作的不同阶段存储不同数据的锁存器。 准备阶段是在程序阶段之后和程序验证阶段之后的当前多阶段程序操作。 对于准备阶段，控制电路使锁存器存储指示在本多阶段程序操作之后的随后的多相程序操作中是否对存储单元进行编程的准备数据。 程序验证阶段的结果以及当前多阶段程序操作开始时的锁存器的内容足以确定准备数据。