Abstract:
A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.
Abstract:
The present invention provides a processing system and associated method; the processing system includes a processing unit, a peripheral unit consuming system resource, a support unit capable of providing the system resource, a buffer capable of storing a portion of the system resource, and a system power manager (SPM). When the processing unit suspends for idle, the peripheral unit consumes the buffer and thus does not need system resource from the support unit, so the support unit and/or the corresponding system resource can be powered down. When the buffer is consumed, the SPM is capable of allocating the system resource for the peripheral unit in response to request of the peripheral unit, so the processing unit does not have to leave idle for allocating the system resource.