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公开(公告)号：US20240385674A1
公开(公告)日：2024-11-21
申请号：US18547130
申请日：2023-02-10
Applicant: MediaTek Inc.
Inventor： Chien-Nan Lin , You-Ming Tsao , Yung-Hsin Chu , An-Li Wang , Yu-Ting Kuo
Abstract: A computing system performs balanced power management based on requirements of graphics scenes in a video game. Based on the requirements of the graphics scenes, the system selects one or more performance metrics to reduce in real-time, where the performance metrics are indicators of video game quality. The system compares estimated power consumption with a power budget after reducing the one or more performance metrics. Based on the requirements of the graphics scenes, the system further selects one or more quality enhancers to activate in real-time while keeping the estimated power consumption within the power budget. Each quality enhancer enhances the video game with respect to a performance metric. The system then displays the video game enhanced by the one or more quality enhancers.
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公开(公告)号：US10545530B2
公开(公告)日：2020-01-28
申请号：US15593314
申请日：2017-05-11
Applicant: MEDIATEK INC.
Inventor： You-Ming Tsao , Chun-Liang Chen , Chen-Chia Lee
IPC: G06F13/16 , G06F1/08 , G06F1/324 , G06F1/3296
Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.
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3.发明申请公开(公告)号：US20170248987A1
公开(公告)日：2017-08-31
申请号：US15593314
申请日：2017-05-11
Applicant: MEDIATEK INC.
Inventor： You-Ming Tsao , Chun-Liang Chen , Chen-Chia Lee
CPC classification number: G06F1/08 , G06F1/324 , G06F1/3296 , G06F13/1689 , Y02D10/126
Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.
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公开(公告)号：US20140365730A1
公开(公告)日：2014-12-11
申请号：US14464712
申请日：2014-08-21
Applicant: MEDIATEK INC.
Inventor： You-Ming Tsao , Hsueh-Bing Yen
CPC classification number: G06F12/0893 , G06F12/0806 , G06F12/0848 , G06F13/16 , G06F13/1652 , G06F2212/306 , G06F2212/601
Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.
Abstract translation: 用于执行动态配置的方法包括：通过暂停从至少一个核/处理器到动态的部分的请求来将动态可配置高速缓存的一部分与多个核/处理器中的至少一个之间的总线冻结 在总线冻结期间可配置缓存，其中所述多个核心/处理器被允许访问所述动态可配置高速缓存，并且所述多个核心/处理器中的所述至少一个核/处理器被允许访问所述动态可配置高速缓存的所述部分; 以及调整所述动态可配置高速缓存的所述部分的大小，其中所述动态可配置高速缓存的所述部分能够高速缓存/存储所述多个核心/处理器中的所述至少一个核心/处理器的信息。 还提供了一种相关联的装置。 特别地，该装置包括多个核心/处理器，动态可配置高速缓存和动态可配置高速缓存控制器，并且可以根据该方法进行操作。
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公开(公告)号：US20240346741A1
公开(公告)日：2024-10-17
申请号：US18626411
申请日：2024-04-04
Applicant: Mediatek Inc.
Inventor： Chengping Luo , You-Ming Tsao , Bozhan Chen , Sheng-Wen Huang
IPC: G06T15/00
CPC classification number: G06T15/005 , G06T2210/12
Abstract: In aspects of the disclosure, a method, a system, and a computer-readable medium, are provided. The method for processing graphics data with a graphics rendering pipeline comprising a mesh shader and a tiler, comprising outputting, by the mesh shader in response to an input of the graphics data, legacy mesh shader output parameters including vertices and primitives, and additional data with a meshlet bounding-box, or axis-aligned bounding box (AABB) structure; sending the AABB to the tiler as an input, and generating, by the tiler, a visibility stream according to the AABB, wherein each entity of the visibility stream indicates that the AABB is fully visible, partially visible, or invisible in the view frustum; and sending the visibility stream back to the tiler as a further input along with the legacy mesh shader output parameters for coming rasterization in a fragment pass.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240144430A1
公开(公告)日：2024-05-02
申请号：US18492836
申请日：2023-10-24
Applicant: MediaTek Inc.
Inventor： Chien-Nan Lin , You-Ming Tsao , Yung-Hsin Chu , An-Li Wang
CPC classification number: G06T3/4053 , G06F11/3062 , G06T3/4046
Abstract: A computing system performs artificial-intelligence (AI) super-resolution (SR). The computing system includes multiple processors, which further includes a graphics processing unit (GPU) and an AI processing unit (APU). The computing system also includes a memory to store AI models. When detecting an indication that the loading of the GPU exceeds a threshold, the processors reduce the resolution of a video output from the GPU in response to the indication. One of the AI models is selected based on graphics scenes in the video and the respective power consumption estimates of the AI models. The processors then perform AI SR operations on the video using the selected AI model to restore the resolution of the video for display.
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公开(公告)号：US20240338881A1
公开(公告)日：2024-10-10
申请号：US18624166
申请日：2024-04-02
Applicant: MEDIATEK INC.
Inventor： Chengping Luo , You-Ming Tsao , Bozhan Chen , Sheng-Wen Huang
CPC classification number: G06T15/005 , G06T15/40 , G06T17/20 , G06T2210/12
Abstract: An application programming interface includes a mesh shader, a rasterizer, and a fragment shader. The mesh shader is used to process 3-dimensional objects and output vertices, primitives, and a plurality of bounding volumes of the 3-dimensional objects. The rasterizer is linked to the mesh shader, and used to project the vertices, the primitives, and the plurality of bounding volumes into 2-dimensional fragments. The fragment shader is linked to the rasterizer, and used to output a 2-dimensional image according to the 2-dimensional fragments.
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8.发明申请INTEGRATED CIRCUIT HAVING AT LEAST ONE FUNCTIONAL CIRCUIT BLOCK OPERATING IN MULTI-SOURCE POWER DOMAIN AND RELATED SYSTEM WITH POWER MANAGEMENT 审中-公开具有电源管理的多源功率域和相关系统中的至少一个功能电路块操作的集成电路公开(公告)号：US20150028940A1
公开(公告)日：2015-01-29
申请号：US14325284
申请日：2014-07-07
Applicant: MEDIATEK INC.
Inventor： You-Ming Tsao , Kin Lam Tong , Chun-Fang Peng
CPC classification number: H01L23/5286 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit has a semiconductor layer, at least one metal layer, a plurality of functional circuit blocks formed on the semiconductor layer, and a power mesh formed on the at least one metal layer. The power mesh has a specific area corresponding to a specific functional circuit block of the functional circuit blocks. The specific area at least has a first power trunk of a first power source and a second power trunk of a second power source distributed therein.
Abstract translation: 集成电路具有半导体层，至少一个金属层，形成在半导体层上的多个功能电路块，以及形成在该至少一个金属层上的功率栅。 功率网具有对应于功能电路块的特定功能电路块的特定区域。 特定区域至少具有分配在其中的第一电源的第一电力中继线和第二电源的第二电力中继线。
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公开(公告)号：US20240386648A1
公开(公告)日：2024-11-21
申请号：US18583884
申请日：2024-02-22
Applicant: MEDIATEK INC.
Inventor： Po-Yu Huang , Shih-Chin Lin , Ching-Yi Tsai , You-Ming Tsao
IPC: G06T15/00
Abstract: A method for performing automatic activation control regarding VRS and associated apparatus are provided. The method applicable to a processing circuit may include: utilizing a rendering classifier to intercept at least one set of original graphic commands on a command path to obtain at least one rendering property, for classifying rendering corresponding to the at least one set of original graphic commands; utilizing the rendering classifier to classify the rendering into at least one predetermined rendering type among multiple predetermined rendering types according to the at least one rendering property, in order to determine at least one shading rate corresponding to the at least one predetermined rendering type for the rendering; and utilizing a shading rate controller to control the processing circuit to selectively activate a VRS function of the processing circuit, for rendering at the at least one shading rate corresponding to the at least one predetermined rendering type.
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公开(公告)号：US09122616B2
公开(公告)日：2015-09-01
申请号：US14464712
申请日：2014-08-21
Applicant: MEDIATEK INC.
Inventor： You-Ming Tsao , Hsueh-Bing Yen
CPC classification number: G06F12/0893 , G06F12/0806 , G06F12/0848 , G06F13/16 , G06F13/1652 , G06F2212/306 , G06F2212/601
Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.
Abstract translation: 用于执行动态配置的方法包括：通过暂停从至少一个核/处理器到动态的部分的请求来将动态可配置高速缓存的一部分与多个核/处理器中的至少一个之间的总线冻结 在总线冻结期间可配置缓存，其中所述多个核心/处理器被允许访问所述动态可配置高速缓存，并且所述多个核心/处理器中的所述至少一个核/处理器被允许访问所述动态可配置高速缓存的所述部分; 以及调整所述动态可配置高速缓存的所述部分的大小，其中所述动态可配置高速缓存的所述部分能够高速缓存/存储所述多个核心/处理器中的所述至少一个核心/处理器的信息。 还提供了一种相关联的装置。 特别地，该装置包括多个核心/处理器，动态可配置高速缓存和动态可配置高速缓存控制器，并且可以根据该方法进行操作。
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