公开(公告)号：US11621920B2

公开(公告)日：2023-04-04

申请号：US17902834

申请日：2022-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Omri Kahalon

IPC: H04L47/20 ,  H04L47/2466 ,  H04L47/2475 ,  G06F9/455 ,  H04L47/783 ,  H04L47/12

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.

公开(公告)号：US11190462B2

公开(公告)日：2021-11-30

申请号：US16693302

申请日：2019-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis

IPC: G06F15/16 ,  H04L12/939 ,  H04L12/861 ,  H04W28/04 ,  H04L29/06 ,  H04L12/879

Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

公开(公告)号：US20210344600A1

公开(公告)日：2021-11-04

申请号：US16865567

申请日：2020-05-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch ,  Eyal Srebro ,  Shay Aisman

IPC: H04L12/801 ,  H04L12/835 ,  H04L12/823

Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.

公开(公告)号：US12130745B2

公开(公告)日：2024-10-29

申请号：US18073586

申请日：2022-12-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Avi Urman

IPC: G06F12/00 ,  G06F12/0802 ,  G06F12/0893 ,  H04L9/06

CPC classification number: G06F12/0893 ,  G06F12/0802 ,  H04L9/0643

Abstract: A caching system operative in conjunction with a memory and a cache, the caching system comprising a processor to use only a single hash function which compresses K bit memory addresses to H_max bit cache addresses, rather than using plural hash functions, to provide perfect hashing for each of plural applications which utilize plural respective subsets, of different sizes, from among 2{circumflex over ( )}H_max cells in the cache; and at least one logic circuit X which receives, as one of its input operands, an output, H_max bits in length, of the single hash function and which generates, as a logic circuit output, a cache address of length H_select to which at least one K-bit address is mapped where H_max

公开(公告)号：US20230269037A1

公开(公告)日：2023-08-24

申请号：US17678074

申请日：2022-02-23

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gil Levy ,  Roni Bar Yanai ,  Avi Urman

IPC: H04L1/20 ,  G06F16/28 ,  G06F16/22

CPC classification number: H04L1/201 ,  G06F16/285 ,  G06F16/2255

Abstract: A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bits. The rules in the corpus conform to respective Rule Patterns (RPs), each RP defining a respective sequence of masked and unmasked bits. The processor is configured to cluster the RPs, using a clustering criterion, into extended Rule Patterns (eRPs) associated with respective hash tables including buckets for storing rule entries. The clustering criterion aims to minimize an overall number of the eRPs while meeting a collision condition that depends on a specified maximal number of rule entries per bucket.

公开(公告)号：US20230239257A1

公开(公告)日：2023-07-27

申请号：US17582047

申请日：2022-01-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Boris Pismenny ,  Ben Ben Ishay ,  Gal Yefet ,  Gil Kremer ,  Avi Urman ,  Yorai Itzhak Zack ,  Khalid Manaa ,  Liran Liss

IPC: H04L49/9057 ,  H04L69/22 ,  H04L49/90

CPC classification number: H04L49/9057 ,  H04L69/22 ,  H04L49/9042

Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

公开(公告)号：US20220417157A1

公开(公告)日：2022-12-29

申请号：US17902834

申请日：2022-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Omri Kahalon

IPC: H04L47/20 ,  H04L47/2466 ,  G06F9/455 ,  H04L47/12 ,  H04L47/2475 ,  H04L47/783

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.

公开(公告)号：US20220231953A1

公开(公告)日：2022-07-21

申请号：US17151705

申请日：2021-01-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Omri Kahalon

IPC: H04L12/813 ,  H04L12/855 ,  H04L12/859 ,  H04L12/801 ,  G06F9/455 ,  H04L12/911

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.

公开(公告)号：US20210328923A1

公开(公告)日：2021-10-21

申请号：US16853783

申请日：2020-04-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Ariel Shahar

IPC: H04L12/743 ,  H04L12/815

Abstract: In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry.

公开(公告)号：US20210297151A1

公开(公告)日：2021-09-23

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04W72/04 ,  H04W74/08 ,  H04L12/931 ,  H04L12/861

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound. packets, which are received from the communication network, depending on the timeslots.