公开(公告)号：US10572400B2

公开(公告)日：2020-02-25

申请号：US15623426

申请日：2017-06-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Finkelstein ,  Lior Narkis ,  Dror Bohrer ,  Roee Moyal

IPC: G06F13/16 ,  G06F13/36 ,  H04L12/801

Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.

公开(公告)号：US20190149486A1

公开(公告)日：2019-05-16

申请号：US16181376

申请日：2018-11-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dror Bohrer ,  Noam Bloch ,  Peter Paneah ,  Richard Graham

IPC: H04L12/879 ,  H04L12/883 ,  H04L12/861 ,  H04L12/935

Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.

公开(公告)号：US20180365176A1

公开(公告)日：2018-12-20

申请号：US15623426

申请日：2017-06-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Finkelstein ,  Lior Narkis ,  Dror Bohrer ,  Roee Moyal

IPC: G06F13/16 ,  H04L12/801 ,  G06F13/36

CPC classification number: G06F13/1642 ,  G06F13/36 ,  H04L47/34

Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.