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公开(公告)号：US20230205873A1
公开(公告)日：2023-06-29
申请号：US17653264
申请日：2022-03-02
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , David Hulton , Jeremy Chritz , Tamara Schmitz , Max S. Vohra
CPC classification number: G06F21/554 , G06N20/00 , G06F3/0655 , G06F3/0604 , G06F3/0673 , G06F2221/034 , G06F9/4411
Abstract: Methods, systems, and devices for training procedure change determination to detect an attack are described. A host device may perform one or more training procedures to train aspects of a memory device (e.g., a dynamic random-access memory (DRAM) component). A training procedure may depend on a current (e.g., present, within a threshold duration) metric associated with the memory device, such as a current channel metric for a channel between the memory device and the host device. The host device, memory device, or another device, may store a set of reference values associated with a training procedure and may compare a result of a training procedure to a reference value of the set to determine whether the training procedure has changed. If the training procedure or a related value has changed, the memory device may disable one or more features of the memory device to protect against a potential attack.
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公开(公告)号：US20220237081A1
公开(公告)日：2022-07-28
申请号：US17721462
申请日：2022-04-15
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
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公开(公告)号：US20220236995A1
公开(公告)日：2022-07-28
申请号：US17680538
申请日：2022-02-25
Applicant: Micron Technology, Inc.
Inventor： Glen E. Hush , Aaron P. Boehm , Fa-Long Luo
Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.
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公开(公告)号：US20220197745A1
公开(公告)日：2022-06-23
申请号：US17690772
申请日：2022-03-09
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.
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公开(公告)号：US20220066701A1
公开(公告)日：2022-03-03
申请号：US17470594
申请日：2021-09-09
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.
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Patent Agency Ranking
公开(公告)号：US11249847B2
公开(公告)日：2022-02-15
申请号：US17216418
申请日：2021-03-29
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
IPC: G06F11/00 , G06F11/10 , H03M13/29 , G11C11/408 , G11C11/4091 , G11C11/22
Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.
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公开(公告)号：US20220030061A1
公开(公告)日：2022-01-27
申请号：US17496034
申请日：2021-10-07
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm
IPC: H04L29/08 , G06F15/173 , H04W4/46
Abstract: Apparatuses, systems, and methods related to a data center using a memory pool between selected memory resources are described. A data center using a memory pool between selected memory resources may enable performance of functions, including automated functions critical for prevention of damage to product, personal safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, a method described herein includes transmitting, from a processor at a first vehicle that comprises the processor and memory, a request to access a pool of memory resources configured from a plurality of vehicles each having a local processor and memory, receiving, from a second vehicle of the plurality of vehicles, an indication to access the pool of memory resources, and reading data from or writing data to the memory at the second vehicle using the processor at the first vehicle based at least in part on receiving the indication to access the pool of memory resources.
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公开(公告)号：US20220027306A1
公开(公告)日：2022-01-27
申请号：US17494980
申请日：2021-10-06
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm
IPC: G06F15/173 , H04L29/08
Abstract: Apparatuses, systems, and methods related to memory pooling between selected memory resources via a base station are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a first memory resource, a first processor coupled to the first memory resource, and a wireless base station coupled to the first processor. The first memory resource, the first processor, and the base station are configured to enable formation of a memory pool between the first memory resource and a second memory resource at a vehicle responsive to a request to access the second memory resource from the first processor transmitted via the base station.
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公开(公告)号：US20210350843A1
公开(公告)日：2021-11-11
申请号：US17384013
申请日：2021-07-23
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
IPC: G11C11/406
Abstract: Methods, systems, and devices for refresh rate control for a memory device are described. For example, a memory array of a memory device may be refreshed according to a first set of refresh parameters, such as a refresh rate. The memory device may detect an event at the memory device associated with a reduction in data integrity. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. As a result of detecting the event, the memory device may adapt one or more of the set of refresh parameters, such as increasing the refresh rate for the memory array. In some cases, the memory device may adapt the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both.
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公开(公告)号：US20210318928A1
公开(公告)日：2021-10-14
申请号：US17216418
申请日：2021-03-29
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.
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