公开(公告)号：US20190171567A1

公开(公告)日：2019-06-06

申请号：US16272945

申请日：2019-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi ,  Chee Weng Tan ,  Sebastien LeMarie ,  Andre Klindworth

IPC: G06F12/0804 ,  G06F13/00 ,  G06F13/16 ,  G06F12/0891

Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus mau include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

公开(公告)号：US10067764B2

公开(公告)日：2018-09-04

申请号：US15646874

申请日：2017-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C13/00 ,  G06F9/30

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

公开(公告)号：US20170308382A1

公开(公告)日：2017-10-26

申请号：US15646874

申请日：2017-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

IPC: G06F9/30 ,  G11C13/00 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10

CPC classification number: G06F9/30047 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/1063 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/2272

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

公开(公告)号：US20140122814A1

公开(公告)日：2014-05-01

申请号：US13840929

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

IPC: G06F9/30

CPC classification number: G06F9/30047 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/1063 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/2272

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

Abstract translation: 描述用于执行存储器操作的装置和方法。 示例性装置包括存储器操作控制器。 存储器操作控制器被配置为接收存储器指令并对其进行解码以提供用于对存储器指令执行存储器操作的内部信号。 存储器操作控制器还被配置为在可变等待时间周期期间提供指示存储器指令的可变等待时间周期的时间的信息。 在示例性方法中，在存储器处接收要写入数据的写指令和地址，并且提供指示用于写指令的可变等待时间周期结束的确认。 在确认之后等待可变总线周转后，接收写入指令的写入数据。