公开(公告)号：US20210090634A1

公开(公告)日：2021-03-25

申请号：US16576621

申请日：2019-09-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Homare Sato

IPC: G11C11/4076 ,  H01L25/065

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.

公开(公告)号：US10553263B2

公开(公告)日：2020-02-04

申请号：US16225303

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC: G11C7/22 ,  G11C16/32 ,  G11C19/28 ,  G11C7/10

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

公开(公告)号：US20190115057A1

公开(公告)日：2019-04-18

申请号：US15783606

申请日：2017-10-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Homare Sato ,  Chiaki Dono ,  Chikara Kondo

IPC: G11C7/22 ,  H03K3/037

Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second dock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.

公开(公告)号：US10262704B1

公开(公告)日：2019-04-16

申请号：US15783606

申请日：2017-10-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Homare Sato ,  Chiaki Dono ,  Chikara Kondo

IPC: G11C8/00 ,  G11C7/22 ,  H03K3/037

Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.

公开(公告)号：US10185652B2

公开(公告)日：2019-01-22

申请号：US15606956

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Homare Sato ,  Chikara Kondo

IPC: G11C7/06 ,  G06F12/02 ,  H01L23/522

Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

公开(公告)号：US20180357156A1

公开(公告)日：2018-12-13

申请号：US16107963

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Seiji Narui ,  Homare Sato ,  Chikara Kondo

IPC: G06F12/02 ,  H01L23/522

CPC classification number: G06F12/02 ,  G06F2212/1016 ,  G06F2212/1028 ,  H01L23/5226

Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.