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公开(公告)号:US10553263B2
公开(公告)日:2020-02-04
申请号:US16225303
申请日:2018-12-19
发明人: Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
摘要: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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公开(公告)号:US20180151207A1
公开(公告)日:2018-05-31
申请号:US15365563
申请日:2016-11-30
发明人: Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
CPC分类号: G11C7/1087 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C19/28 , G11C2207/108 , G11C2207/2272
摘要: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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公开(公告)号:US10163469B2
公开(公告)日:2018-12-25
申请号:US15365563
申请日:2016-11-30
发明人: Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
摘要: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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公开(公告)号:US09934832B2
公开(公告)日:2018-04-03
申请号:US15635071
申请日:2017-06-27
发明人: Tomoyuki Shibata , Minehiko Uehara
CPC分类号: G11C7/222 , G11C5/025 , G11C5/06 , G11C7/106 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C8/18 , G11C29/023 , G11C29/028 , H01L23/481 , H01L23/528 , H01L25/0657 , H01L25/18 , H01L2225/06541 , H03K5/13 , H03K5/14 , H03K5/1565 , H03K5/24 , H03K5/26
摘要: Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.
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公开(公告)号:US20170309319A1
公开(公告)日:2017-10-26
申请号:US15635071
申请日:2017-06-27
发明人: Tomoyuki Shibata , Minehiko Uehara
CPC分类号: G11C7/222 , G11C5/025 , G11C5/06 , G11C7/106 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C8/18 , G11C29/023 , G11C29/028 , H01L23/481 , H01L23/528 , H01L25/0657 , H01L25/18 , H01L2225/06541 , H03K5/13 , H03K5/14 , H03K5/1565 , H03K5/24 , H03K5/26
摘要: Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.
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公开(公告)号:US09722588B1
公开(公告)日:2017-08-01
申请号:US15138042
申请日:2016-04-25
发明人: Tomoyuki Shibata , Minehiko Uehara
IPC分类号: H03B19/00 , H03K5/14 , H01L23/48 , H01L23/528 , H01L25/065 , H01L25/18 , G11C5/02 , G11C5/06 , G11C8/18 , G11C7/10 , H03K5/24 , H03K5/156
CPC分类号: G11C7/222 , G11C5/025 , G11C5/06 , G11C7/106 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C8/18 , G11C29/023 , G11C29/028 , H01L23/481 , H01L23/528 , H01L25/0657 , H01L25/18 , H01L2225/06541 , H03K5/13 , H03K5/14 , H03K5/1565 , H03K5/24 , H03K5/26
摘要: Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.
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公开(公告)号:US10943625B2
公开(公告)日:2021-03-09
申请号:US16721515
申请日:2019-12-19
发明人: Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
摘要: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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公开(公告)号:US20190122708A1
公开(公告)日:2019-04-25
申请号:US16225303
申请日:2018-12-19
发明人: Chikara Kondo , Tomoyuki Shibata , Chiaki Dono , Seiji Narui , Minehiko Uehara , Taihei Shido , Homare Sato
摘要: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
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