公开(公告)号：US11868827B1

公开(公告)日：2024-01-09

申请号：US17866350

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/54 ,  G06F13/16

CPC classification number: G06F9/546 ,  G06F13/1668

Abstract: A storage product having: a network interface operable on a computer network; a bus connector adapted to be connected to a computer bus; a storage device having a storage capacity accessible through network storage services provided over the network interface; and a processing device configured to at least generate storage access messages from incoming packets received by the network interface from the computer network. The storage product is operable in a standalone mode when no local host system is connected to the bus connector to control the storage product and operable in a slave mode when a local host system is connected to the bus connector to process a portion of the storage access messages.

公开(公告)号：US11816345B2

公开(公告)日：2023-11-14

申请号：US17301213

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Kumar V K H Kanteti ,  Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/064 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0688

Abstract: A memory sub-system can determine a block granularity for an input/output (I/O) data stream received from a host system. The memory sub-system can determine that the block granularity is different than a memory block granularity of a first memory region in a first namespace of the one or more memory devices, where the first memory region is to store the I/O data stream. The memory sub-system can accumulate blocks from the I/O data stream in a second memory region in a second namespace of the one or more memory devices. Responsive to a capacity of the accumulated blocks in the second memory region satisfying a threshold criterion, the memory sub-system can migrate the accumulated plurality of blocks from the second memory region to the first memory region.

公开(公告)号：US11775188B2

公开(公告)日：2023-10-03

申请号：US17591548

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph Harold Steinmetz

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0608 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679

Abstract: An apparatus with a solid state drive (SSD) configured to manage storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands and the write commands. In response to an indication of a storage space request for the host system, the apparatus identifies an application using a proof of space plot stored in a portion of the solid state drive, requests the application to separate from the proof of space plot, and then delete a namespace in which the proof of space plot is stored to release storage resources occupied by the proof of space plot to meet the storage space request.

公开(公告)号：US20230297286A1

公开(公告)日：2023-09-21

申请号：US18200851

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph H. Steinmetz

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0679 ,  G06F3/0604

Abstract: A host command is received designating a first interface standard at a first port for exposing a storage element implemented by a non-volatile memory device and a second interface standard at a second port for exposing a persistent memory region (PMR) implemented as a power protected region of a volatile memory device. The non-volatile memory device and the volatile memory device are associated with a first switch for implementing the first interface standard and a second switch for implementing the second interface standard. The first interface standard supports one or more alternate protocols implemented by the second interface standard. The storage element is exposed by designating the first interface standard at the first port and the PMR by designating the second interface standard at the second port. A segment of the PMR is allocated as a cacheable memory marked as visible through, and shared through, the second interface standard.

公开(公告)号：US20230266897A1

公开(公告)日：2023-08-24

申请号：US17680183

申请日：2022-02-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0683

Abstract: A system includes one or more memory devices and a processing device coupled to the memory device(s) to perform operations including receiving a first set of data items from a host system to be programmed to the one or more memory devices. The operations include determining, in view of a first zone group identifier associated with the first set of data items, that each data item of the first set of data items is to be programed to one or more zones associated with a first zone group identified by the first zone group identifier. The operations include identifying a first set of zones across the one or more memory devices that match a size associated with the first zone group and that satisfy a programming parallelism criterion. The operations include programming each of the first set of data items to memory cells residing at the identified first set of zones.

公开(公告)号：US11687244B2

公开(公告)日：2023-06-27

申请号：US16663029

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, a function of the plurality of functions receives input/output (I/O) operations from a host computing system. The processing device further selects a first function of the plurality of functions to service and assigns a first operation weight to a first I/O operation type of I/O operations received at the first function and a second operation weight to a second I/O operation type of I/O operations received at the first function. The processing device also selects, for execution, a first number of operations of the first I/O operation type of the I/O operations received at the first function according to the first operation weight and a second number of operations of the second I/O operation type of the I/O operations received at the first function according to the second operation weight. The processing device then executes the first number of operations and the second number of operations at the memory device.

公开(公告)号：US20230188599A1

公开(公告)日：2023-06-15

申请号：US17551024

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph Harold Steinmetz

IPC: G06F3/06 ,  H04L67/104

CPC classification number: G06F3/0631 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/067 ,  H04L67/104

Abstract: An apparatus with a solid state drive (SSD) having firmware to perform peer to peer transfer of proof of space plots. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD according to configuration data to: identify an opportunity for a transfer of a proof of space plot; establish a peer to peer connection to a device that is separate from the solid state drive; and transfer, over the peer to peer connection, the proof of space plot between the solid state drive and the device.

公开(公告)号：US20230188337A1

公开(公告)日：2023-06-15

申请号：US17550828

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph Harold Steinmetz

IPC: H04L9/08 ,  H04L9/30 ,  G06F3/06

CPC classification number: H04L9/088 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0679 ,  H04L9/30

Abstract: A security server storing a plurality of cryptographic keys to support device authentication, access control and proof of space plot farming. The cryptographic keys can include a first cryptographic key representative of an identity of a memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots. The security server can sign blocks in a blockchain created via plots in the pool, sign commands to access the memory region, and secure transfer of the second and/or third cryptographic key to the computer operated by an owner of the memory device.

公开(公告)号：US20230043418A1

公开(公告)日：2023-02-09

申请号：US17514267

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  Ali Mohammadzadeh ,  Dheeraj Srinivasan ,  Daniel J. Hubbard ,  Luca Bert

IPC: G06F3/06

Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

公开(公告)号：US20220398045A1

公开(公告)日：2022-12-15

申请号：US17893102

申请日：2022-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F12/10

Abstract: A memory device comprises a file system and a processing device to perform operations comprising receiving, from the file system, a first data access command comprising a payload, responsive to receiving the first data access command, determining, using the file system, a characteristic of the payload, wherein the characteristic of the payload indicates whether the first data access command is for data or for metadata, and sending a second data access command to a memory sub-system, wherein the second data access command includes an indication of a memory region of a memory device in which the memory sub-system is to store the payload, wherein the indication of the memory region is based on the characteristic of the payload.