公开(公告)号：US11074126B2

公开(公告)日：2021-07-27

申请号：US16509417

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Randall J. Rooney

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G11C13/00

Abstract: An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

公开(公告)号：US20210165655A1

公开(公告)日：2021-06-03

申请号：US17156065

申请日：2021-01-22

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F9/30 ,  G06F3/06 ,  G06F30/331

Abstract: Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

公开(公告)号：US20210072287A1

公开(公告)日：2021-03-11

申请号：US16985156

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Stewart ,  Eric J. Stave ,  Matthew A. Prather

IPC: G01R13/32 ,  H04L1/24 ,  H04L1/20

Abstract: A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.

公开(公告)号：US20210057003A1

公开(公告)日：2021-02-25

申请号：US16815999

申请日：2020-03-11

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C11/4093 ,  G06F11/30

Abstract: Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

公开(公告)号：US20210034554A1

公开(公告)日：2021-02-04

申请号：US17074281

申请日：2020-10-19

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Frank F. Ross ,  Randall J. Rooney

IPC: G06F13/16 ,  G11C11/406 ,  G11C7/22 ,  G06F3/06 ,  G06F13/40

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

公开(公告)号：US20200278940A1

公开(公告)日：2020-09-03

申请号：US16289967

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F3/06 ,  G11C5/04

Abstract: The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

公开(公告)号：US10754801B2

公开(公告)日：2020-08-25

申请号：US16846146

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G11C5/14 ,  G06F13/16 ,  G06F1/3206 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US20200218476A1

公开(公告)日：2020-07-09

申请号：US16820319

申请日：2020-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew A. Prather

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

公开(公告)号：US10552087B2

公开(公告)日：2020-02-04

申请号：US16030740

申请日：2018-07-09

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Frank F. Ross ,  Randall J. Rooney

IPC: G11C7/00 ,  G06F3/06 ,  G11C11/406 ,  G06F13/40

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

公开(公告)号：US20190369915A1

公开(公告)日：2019-12-05

申请号：US16030740

申请日：2018-07-09

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Frank F. Ross ,  Randall J. Rooney

IPC: G06F3/06 ,  G11C11/406 ,  G06F13/40

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.