公开(公告)号：US11556267B2

公开(公告)日：2023-01-17

申请号：US17006978

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo′ Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.

公开(公告)号：US11443812B2

公开(公告)日：2022-09-13

申请号：US17127358

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Scott A. Stoller ,  Pitamber Shukla ,  Priya Venkataraman ,  Giuseppina Puzzilli ,  Niccolo′ Righetti

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.

公开(公告)号：US09214389B2

公开(公告)日：2015-12-15

申请号：US14265168

申请日：2014-04-29

Applicant: Micron Technology, Inc.

Inventor： Niccolo′ Righetti ,  Sara Vigano ,  Emilio Camerlenghi

IPC: H01L21/76 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

Abstract translation: 一些实施例包括形成存储器阵列的方法。 形成了在较低水平上具有较高水平的组件。 下层包括电路。 上层包括存储器阵列区域内的半导体材料，并且在存储器阵列区域周围的区域中包括绝缘材料。 第一和第二沟槽形成为延伸到半导体材料中。 第一和第二沟槽将半导体材料图案化成多个基座。 第二沟槽延伸到周边区域。 在周边区域内形成接触开口以从第二沟槽延伸到电路的第一级。 导电材料形成在第二沟槽内部和接触开口内。 导电材料在第二沟槽内形成感测/接入线，并在接触开口内形成电接触，以将感测/接入线电耦合到较低级别的电路。