公开(公告)号：US11899961B2

公开(公告)日：2024-02-13

申请号：US17652229

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US11416422B2

公开(公告)日：2022-08-16

申请号：US16573780

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean S. Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06K7/08 ,  G06K19/06 ,  G06F13/10 ,  G06F3/06 ,  G06F13/12 ,  G06F12/0802

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

公开(公告)号：US11269780B2

公开(公告)日：2022-03-08

申请号：US16573541

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Sean S. Eilert ,  Hongyu Wang ,  Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Justin M. Eno ,  Shivam Swami

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).

公开(公告)号：US20210193209A1

公开(公告)日：2021-06-24

申请号：US16719907

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).

公开(公告)号：US20210081353A1

公开(公告)日：2021-03-18

申请号：US16573795

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Justin M. Eno ,  Kenneth Marion Curewitz ,  Sean S. Eilert

IPC: G06F15/78 ,  G06F9/30

Abstract: An accelerator chip, e.g., an artificial intelligence (AI) accelerator chip, that can connect a system on a chip (SoC) and a memory chip. The accelerator chip can have a first set of pins configured to connect to the memory chip via wiring, as well as a second set of pins configured to connect to the SoC via wiring. The accelerator chip can be configured to perform and accelerate application-specific computations (e.g., AI computations) for the SoC, as well as use the memory chip as memory for the application-specific computations. For example, the accelerator chip can be an AI accelerator chip and the AI accelerator chip can be configured to perform and accelerate AI computations for the SoC, as well as use the memory chip as memory for the AI computations.

公开(公告)号：US20210081337A1

公开(公告)日：2021-03-18

申请号：US16573805

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth Marion Curewitz ,  Justin M. Eno

IPC: G06F13/16 ,  G06F9/30

Abstract: A memory chip (e.g., DRAM) connecting a SoC and an accelerator chip (e.g., an AI accelerator chip). A system including the memory chip and the accelerator chip. The system can include the SoC. The memory chip can include first memory cells to store and provide computation input data (e.g., AI computation input data) received from the SoC to be used by the accelerator chip as computation input (e.g., AI computation input). The memory chip can include second memory cells to store and provide first computation output data (e.g., AI computation output data) received from the accelerator chip to be retrieved by the SoC or reused by the accelerator chip as computation input. The memory chip can also include third memory cells to store second computation output data (e.g., non-AI computation output data) related to non-AI tasks received from the SoC to be retrieved by the SoC for non-AI tasks.

公开(公告)号：US20210081336A1

公开(公告)日：2021-03-18

申请号：US16573780

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean S. Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F13/10 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/12

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

公开(公告)号：US20210073622A1

公开(公告)日：2021-03-11

申请号：US16887665

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06F12/06 ,  G06N3/04

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

公开(公告)号：US20210064455A1

公开(公告)日：2021-03-04

申请号：US16553731

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F11/07 ,  G06F11/10 ,  G11C11/409 ,  G11C5/06 ,  G11C15/04

Abstract: Methods, systems, and devices for error correction for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.

公开(公告)号：US10089043B2

公开(公告)日：2018-10-02

申请号：US13842984

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Sean S. Eilert

IPC: G06F12/00 ,  G06F3/06

Abstract: Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system coupled to the processor. The memory system is configured to receive instructions from the processor to access information stored by the memory system. The memory system includes a plurality of memory nodes, wherein each memory node of the plurality of memory nodes is coupled to at least one other memory node of the plurality of memory nodes, and each memory node of the plurality of memory nodes is configured to generate an internal message including instructions for an operation, the internal message to be provided to another memory node of the plurality of memory nodes to perform the operation.