公开(公告)号：US11615828B2

公开(公告)日：2023-03-28

申请号：US17524514

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Hiroshi Akamatsu ,  Takamasa Suzuki ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/4074 ,  G06F11/30 ,  G11C5/14

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

公开(公告)号：US20230068011A1

公开(公告)日：2023-03-02

申请号：US17895565

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara ,  Yusuke Yono ,  Donald Martin Morgan ,  Nobuo Yamamoto

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/18

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：US11462249B2

公开(公告)日：2022-10-04

申请号：US16916612

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara ,  Yusuke Jono ,  Donald Martin Morgan ,  Nobuo Yamamoto

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/18

Abstract: Methods, systems, and devices for reading and writing memory management data using a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：US20220246219A1

公开(公告)日：2022-08-04

申请号：US17675622

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

IPC: G11C16/30 ,  G11C16/12 ,  G11C7/20 ,  G11C16/04 ,  G11C16/32 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/417

Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

公开(公告)号：US20210210158A1

公开(公告)日：2021-07-08

申请号：US17150902

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara

IPC: G11C29/00 ,  G06F11/10

Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.

公开(公告)号：US20210210131A1

公开(公告)日：2021-07-08

申请号：US17211556

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US10984848B2

公开(公告)日：2021-04-20

申请号：US16793889

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US10607678B2

公开(公告)日：2020-03-31

申请号：US16269485

申请日：2019-02-06

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US11742013B2

公开(公告)日：2023-08-29

申请号：US17211556

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US20220076725A1

公开(公告)日：2022-03-10

申请号：US17524514

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Hiroshi Akamatsu ,  Takamasa Suzuki ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/4074 ,  G06F11/30

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.