公开(公告)号：US20150085561A1

公开(公告)日：2015-03-26

申请号：US14495775

申请日：2014-09-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akiko Maeda ,  Shuichi Tsukada ,  Yusuke Jono

IPC: G11C13/00 ,  G11C29/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/004 ,  G11C16/20 ,  G11C29/70 ,  G11C2013/0054 ,  G11C2013/0083 ,  G11C2013/009

Abstract: A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.

Abstract translation: 半导体器件包括存储单元阵列，其包括多个第一和第二存储器单元，每个存储器单元包括可变电阻元件，该可变电阻元件建立响应于在施加形成电压之后施加写入电压而改变的电阻，第一存储器 施加成形电压的单元和不施加形成电压的第二存储单元，并且第二存储单元被配置为存储构成第一信息的第一和第二逻辑值之一，第一和第二逻辑值为 彼此不同。

公开(公告)号：US11721372B2

公开(公告)日：2023-08-08

申请号：US17895565

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara ,  Yusuke Jono ,  Donald Martin Morgan ,  Nobuo Yamamoto

IPC: G11C7/20 ,  G11C11/22 ,  G11C7/06 ,  G11C7/10 ,  G11C7/18

CPC classification number: G11C7/065 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/18 ,  G11C7/20

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：US20210407556A1

公开(公告)日：2021-12-30

申请号：US16916612

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara ,  Yusuke Jono ,  Donald Martin Morgan ,  Nobuo Yamamoto

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/18 ,  G11C7/20

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：US11462249B2

公开(公告)日：2022-10-04

申请号：US16916612

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara ,  Yusuke Jono ,  Donald Martin Morgan ,  Nobuo Yamamoto

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/18

Abstract: Methods, systems, and devices for reading and writing memory management data using a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：US09236123B2

公开(公告)日：2016-01-12

申请号：US14495775

申请日：2014-09-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akiko Maeda ,  Shuichi Tsukada ,  Yusuke Jono

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04 ,  G11C16/20 ,  G11C29/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/004 ,  G11C16/20 ,  G11C29/70 ,  G11C2013/0054 ,  G11C2013/0083 ,  G11C2013/009

Abstract: A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.

Abstract translation: 半导体器件包括存储单元阵列，其包括多个第一和第二存储器单元，每个存储器单元包括可变电阻元件，该可变电阻元件建立响应于在施加形成电压之后施加写入电压而改变的电阻，第一存储器 施加成形电压的单元和不施加形成电压的第二存储单元，并且第二存储单元被配置为存储构成第一信息的第一和第二逻辑值之一，第一和第二逻辑值为 彼此不同。