公开(公告)号：US20240144984A1

公开(公告)日：2024-05-02

申请号：US18051143

申请日：2022-10-31

Applicant: Micron Technology, Inc.

Inventor： Yoshihito Morishita

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1084 ,  G11C7/1057 ,  G11C7/22

Abstract: Devices and methods for operating a low-power memory device includes a first data input (DQ) circuitry including an input buffer configured to generate a loopback data signal based at least in part on a data signal received at the first DQ circuitry when the low-power memory device operates in a feedback mode. A second DQ circuitry includes an output buffer configured to receive the loopback data signal from the first DQ circuitry and to output the loopback data signal via a data pin.

公开(公告)号：US11830565B2

公开(公告)日：2023-11-28

申请号：US17736585

申请日：2022-05-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihito Morishita ,  Hiroshi Ichikawa

IPC: G11C11/4096 ,  G11C29/52 ,  G11C11/4093

CPC classification number: G11C29/52 ,  G11C11/4093 ,  G11C11/4096

Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

公开(公告)号：US11545210B2

公开(公告)日：2023-01-03

申请号：US17446569

申请日：2021-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihito Morishita ,  Chikara Kondo

IPC: G11C11/4078 ,  H04L9/06 ,  G11C29/02 ,  G11C11/408

Abstract: Apparatuses, systems, and methods for fuse based device identification. A device may include a number of fuses which are used to encode permanent information on the device. The device may receive an identification request, and may generate an identification number based on the states of at least a portion of the fuses. For example, the device may include a hash generator, which may generate the identification number by using the fuse information as a seed for a hash algorithm.

公开(公告)号：US20220165350A1

公开(公告)日：2022-05-26

申请号：US17105137

申请日：2020-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihito Morishita ,  Hiroshi Ichikawa

IPC: G11C29/52 ,  G11C11/4093 ,  G11C11/4096

Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

公开(公告)号：US11270758B2

公开(公告)日：2022-03-08

申请号：US16942503

申请日：2020-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Yoshihito Morishita ,  Daigo Toyama ,  Takamasa Suzuki

IPC: G11C7/00 ,  G11C11/408 ,  G11C11/406

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.