公开(公告)号：US11830565B2

公开(公告)日：2023-11-28

申请号：US17736585

申请日：2022-05-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihito Morishita ,  Hiroshi Ichikawa

IPC: G11C11/4096 ,  G11C29/52 ,  G11C11/4093

CPC classification number: G11C29/52 ,  G11C11/4093 ,  G11C11/4096

Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

公开(公告)号：US20220165350A1

公开(公告)日：2022-05-26

申请号：US17105137

申请日：2020-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihito Morishita ,  Hiroshi Ichikawa

IPC: G11C29/52 ,  G11C11/4093 ,  G11C11/4096

Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

公开(公告)号：US20240244836A1

公开(公告)日：2024-07-18

申请号：US18622235

申请日：2024-03-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hidenori Yamaguchi ,  Katsumi Koge ,  Junya Suzuki ,  Hiroshi Ichikawa

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.

公开(公告)号：US20220406792A1

公开(公告)日：2022-12-22

申请号：US17355006

申请日：2021-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hidenori Yamaguchi ,  Katsumi Koge ,  Junya Suzuki ,  Hiroshi Ichikawa

IPC: H01L27/108

Abstract: A semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.

公开(公告)号：US20220262451A1

公开(公告)日：2022-08-18

申请号：US17736585

申请日：2022-05-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihito Morishita ,  Hiroshi Ichikawa

IPC: G11C29/52 ,  G11C11/4096 ,  G11C11/4093

Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

公开(公告)号：US11348660B1

公开(公告)日：2022-05-31

申请号：US17105137

申请日：2020-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihito Morishita ,  Hiroshi Ichikawa

IPC: G11C11/4096 ,  G11C29/52 ,  G11C11/4093

Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.