公开(公告)号：US20140122777A1

公开(公告)日：2014-05-01

申请号：US13836113

申请日：2013-03-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： HakJune OH ,  Jin-Ki KIM ,  Young Goan KIM ,  Hyun Woong LEE

IPC: G06F3/06

CPC classification number: G06F3/0661 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/1694

Abstract: A memory controller of a data storage device which communicates with a host, has channel control modules each being configurable to have at three different pinout assignments for interfacing with two different types of memory devices operating with different memory interface protocols. One pinout assignment corresponds to a memory interface protocol where memory devices can be connected in parallel with each other. Two other pinout assignments correspond respectively to inbound and outbound signals of another memory interface protocol where memory devices are serially connected with each other. In this mode of operation, one channel control module is configured to provide the outbound signals while another channel control module is configured to receive the inbound signals. Each memory port of the channel control modules includes port buffer circuitry configurable for different functional signal assignments. The configuration of each channel control module is selectable by setting predetermined ports or registers.

Abstract translation: 与主机通信的数据存储设备的存储器控​​制器具有通道控制模块，每个通道控制模块可配置为具有三种不同的引脚分配，用于与使用不同存储器接口协议操作的两种不同类型的存储器件进行接口。 一个引脚分配对应于存储器设备可以彼此并联连接的存储器接口协议。 另外两个引脚分配分别对应于另一存储器接口协议的入站和出站信号，其中存储器设备彼此串联连接。 在这种操作模式中，一个信道控制模块被配置为提供出站信号，而另一个信道控制模块被配置为接收入站信号。 信道控制模块的每个存储器端口包括可配置用于不同功能信号分配的端口缓冲器电路。 每个通道控制模块的配置可以通过设置预定的端口或寄存器来选择。

公开(公告)号：US20140082260A1

公开(公告)日：2014-03-20

申请号：US13835968

申请日：2013-03-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： HakJune OH ,  Jin-Ki KIM ,  Young Goan KIM ,  Hyun Woong LEE

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/385

Abstract: A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller.

Abstract translation: 与主机进行通信的数据存储设备的存储器控​​制器可配置为具有用于与相应不同类型的存储器件接口的至少两个不同的引脚分配。 每个引脚分配对应于特定的存储器接口协议。 存储器控制器的每个存储器接口端口基于所使用的选择的存储器接口协议，包括可配置用于不同功能信号分配的端口缓冲器电路。 通过设置存储器控制器的预定端口或寄存器来选择每个存储器接口端口的接口电路配置。

公开(公告)号：US20130170298A1

公开(公告)日：2013-07-04

申请号：US13776757

申请日：2013-02-26

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON ,  Steven PRZYBYLSKI

IPC: G11C16/10

CPC classification number: G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

Abstract translation: 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。