SCALABLE MEMORY SYSTEM
    1.
    发明申请
    SCALABLE MEMORY SYSTEM 审中-公开
    可扩展存储系统

    公开(公告)号:US20140195715A1

    公开(公告)日:2014-07-10

    申请号:US14172946

    申请日:2014-02-05

    Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

    Abstract translation: 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性,可以包含任何数量的内存设备,而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令,其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码,使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号,用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作,以进一步提高性能。

    ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS
    2.
    发明申请
    ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS 有权
    具有不完全错误特性的通道和存储器的错误检测和校正码

    公开(公告)号:US20130232393A1

    公开(公告)日:2013-09-05

    申请号:US13865514

    申请日:2013-04-18

    Abstract: A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.

    Abstract translation: 通道具有第一和第二端。 信道的第一端耦合到发射机。 信道能够发送从从第一端到第二端的符号集中选择的符号。 该通道显示不完整的错误引入属性。 代码包括一组代码字。 代码字集合的元素是一个或多个代码符号。 代码符号是符号集的成员。 根据信道的误差引入属性,码集集合的元素之间的最小修改汉明距离大于码集集合元素之间的最小汉明距离。 还描述了存储器件,使用该通道的方法以及生成代码的方法。

    RING-OF-CLUSTERS NETWORK TOPOLOGIES
    3.
    发明申请
    RING-OF-CLUSTERS NETWORK TOPOLOGIES 有权
    环网络网络拓扑

    公开(公告)号:US20140115190A1

    公开(公告)日:2014-04-24

    申请号:US14057102

    申请日:2013-10-18

    Abstract: In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.

    Abstract translation: 在集群中的网络拓扑结构中,并行访问从属设备组,使得环周围的延迟与集群的数量成比例,与集成电路的数量成正比。 集群的设备共享输入和输出环段,使得到达输入段的数据包被集群中的所有设备接收和解释。 在其他实施例中,每个群集中的一个或全部除了一个从设备是睡着的或者被禁用的,使得它们不输入和解释传入的分组。 无论如何,在所有实施例中,集群的从站可能在控制器的方向下协作,以确保其中至少一个在任何给定时间主动地驱动输出段。 可以通过设备ID,集群ID或其组合来寻址设备。 本发明的实施例适用于利用多芯片模块实现和垂直电路堆叠的形式。

    SCALABLE MEMORY SYSTEM
    4.
    发明申请
    SCALABLE MEMORY SYSTEM 有权
    可扩展存储系统

    公开(公告)号:US20130170298A1

    公开(公告)日:2013-07-04

    申请号:US13776757

    申请日:2013-02-26

    Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

    Abstract translation: 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性,可以包含任何数量的内存设备,而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令,其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码,使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号,用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作,以进一步提高性能。

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