公开(公告)号：US20140133235A1

公开(公告)日：2014-05-15

申请号：US14158116

申请日：2014-01-17

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM

IPC: G11C16/10

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

Abstract translation: 具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。 每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。 通过选择性地调整存储体的页面大小，相应地调整块大小。

公开(公告)号：US20130070539A1

公开(公告)日：2013-03-21

申请号：US13650580

申请日：2012-10-12

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM ,  HakJune OH

IPC: G11C11/402 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

公开(公告)号：US20130107443A1

公开(公告)日：2013-05-02

申请号：US13665181

申请日：2012-10-31

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM ,  DaeHee YI ,  HyoShin KIM

IPC: G06F1/16

CPC classification number: G11C5/04 ,  G11C7/1003

Abstract: A mass storage memory module system including a memory module having memory holding members which can be connected to each other, and removably connected to a memory controller. One or more modular memory holding members can be connected to each other to expand the overall storage capacity of the memory module. The presently described expandable memory module does not have a storage capacity limit. A memory holding member includes a plate, a plane, a board and another material having at least one memory device, or, on which at least one memory device is held or to which at least one memory device is mounted.

Abstract translation: 一种大容量存储器模块系统，包括具有能够彼此连接的存储器保持部件的存储器模块，并且可移除地连接到存储器控制器。 一个或多个模块化存储器保持构件可以彼此连接以扩展存储器模块的总体存储容量。 目前描述的可扩展存储器模块不具有存储容量限制。 存储器保持构件包括板，平面，板和具有至少一个存储器件的另一种材料，或者在其上保持至少一个存储器件或至少一个存储器件被安装在该存储器件上。

公开(公告)号：US20230253036A1

公开(公告)日：2023-08-10

申请号：US18109390

申请日：2023-02-14

Applicant: Mosaid Technologies Incorporated

Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC: G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/06

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US20210327503A1

公开(公告)日：2021-10-21

申请号：US17246190

申请日：2021-04-30

Applicant: Mosaid Technologies Incorporated

Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC: G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US20140195715A1

公开(公告)日：2014-07-10

申请号：US14172946

申请日：2014-02-05

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON ,  Steven PRZYBYLSKI

IPC: G11C7/10 ,  G06F12/06

CPC classification number: G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

Abstract translation: 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

公开(公告)号：US20140185379A1

公开(公告)日：2014-07-03

申请号：US14197505

申请日：2014-03-05

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM

IPC: G11C14/00

CPC classification number: G11C14/0018 ,  G11C11/005

Abstract: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.

Abstract translation: 提供了用于存储数据的混合固态存储器系统。 固态存储器系统包括易失性固态存储器，非易失性固态存储器和存储器控制器。 此外，提供了一种用于将数据存储在固态存储器系统中的方法。 该方法包括以下步骤。 存储器控制器接收写命令。 响应于写命令，写数据存储在易失性存储器中。 响应于数据传输请求，数据从易失性存储器传送到非易失性存储器。

公开(公告)号：US20140133242A1

公开(公告)日：2014-05-15

申请号：US14156047

申请日：2014-01-15

Applicant: MOSAID Technologies Incorporated

Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC: G11C16/26

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract translation: 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US20140133236A1

公开(公告)日：2014-05-15

申请号：US14159823

申请日：2014-01-21

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom PYEON ,  Jin-Ki KIM

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

Abstract: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.

Abstract translation: 通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。 集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。 对于源行页面编程，分发线可以称为全局公用源线（GCSL）。 在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。 为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。 此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

公开(公告)号：US20140019705A1

公开(公告)日：2014-01-16

申请号：US14027858

申请日：2013-09-16

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom PYEON ,  Jin-Ki KIM ,  Peter B. GILLINGHAM

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

Abstract translation: 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 桥接器件具有组织为存储体的存储器，其中每个存储体被配置为具有小于页面缓冲器的最大物理大小的虚拟页面大小。 因此，只有与存储在页面缓冲器中的虚拟页大小相对应的数据段被传送到存储体。 以具有有序结构的虚拟页面大小（VPS）配置命令提供虚拟页面大小，其中在命令中包含VPS配置代码的VPS数据字段的位置对应于从最不重要的银行排序到不同的银行， 最重要的银行。 VPS配置命令的大小是可变的，并且只包括配置的最高有效存储库的VPS配置代码和较低的重要库。