公开(公告)号：US07155649B2

公开(公告)日：2006-12-26

申请号：US10722752

申请日：2003-11-26

申请人： Toshinobu Nakao ,  Shinji Ozaki ,  Tomohisa Sezaki

发明人： Toshinobu Nakao ,  Shinji Ozaki ,  Tomohisa Sezaki

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/31858 ,  G01R31/318594

摘要： A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n>1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n−1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.

摘要翻译： 扫描测试电路设置有具有n个扫描存储元件（n：整数，n> 1）的扫描链; 扫描时钟生成电路，其能够控制用于将数据移位到第一至第（n-1）个扫描存储元件中的第一时钟的频率，以及用于将数据移位到第二时钟的频率 第n扫描存储元件，并且彼此独立地执行实际操作; 以及扫描选择内部信号产生电路，用于产生与第二时钟同步的扫描选择内部信号。

公开(公告)号：US5835505A

公开(公告)日：1998-11-10

申请号：US843581

申请日：1997-04-16

申请人： Yoshito Nishimichi ,  Satoshi Ogura ,  Shinji Ozaki ,  Seiji Tokunoh ,  Akira Miyoshi ,  Hiroaki Yamamoto ,  Yoshiaki Kasuga

发明人： Yoshito Nishimichi ,  Satoshi Ogura ,  Shinji Ozaki ,  Seiji Tokunoh ,  Akira Miyoshi ,  Hiroaki Yamamoto ,  Yoshiaki Kasuga

IPC分类号： G06F11/36 ,  G01R31/28 ,  G11C29/00

CPC分类号： G06F11/3648

摘要： A semiconductor integrated circuit includes a functional block realizing at least part of a function of the semiconductor integrated circuit. The functional block includes a plurality of basic cells and a plurality of terminal cells. Each of the plurality of terminal cells has a connector for mediating a communication between another semiconductor integrated circuit and one of the plurality of basic cells.

摘要翻译： 半导体集成电路包括实现半导体集成电路的功能的至少一部分的功能块。 功能块包括多个基本单元和多个终端单元。 多个终端单元中的每一个具有用于中介另一半导体集成电路与多个基本单元中的一个之间的通信的连接器。

公开(公告)号：US5754813A

公开(公告)日：1998-05-19

申请号：US811663

申请日：1997-03-05

申请人： Hiroaki Yamamoto ,  Shinji Ozaki ,  Yoshito Nishimichi

发明人： Hiroaki Yamamoto ,  Shinji Ozaki ,  Yoshito Nishimichi

IPC分类号： G06F9/38 ,  G06F9/40

CPC分类号： G06F9/382 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3869

摘要： Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.

摘要翻译： 两个指令执行单元执行不同类型的指令。 提供两个指令选择电路。 两个指令总线耦合到具有预解码器和指令队列的指令备用单元。 指令备用单元通过两条等待指令总线连接到指令选择电路的输入侧。 指令获取控制电路检测任何指令执行单元尚未执行的指令。 这种未执行的指令在指令队列中等待，然后与其预解码结果一起应用于在下一个选择时间被选择的每个指令选择电路。 作为这种安排的结果，可以实现并行执行不同类型指令的快速执行。

公开(公告)号：US4992891A

公开(公告)日：1991-02-12

申请号：US303749

申请日：1989-01-27

申请人： Keiichi Komatsu ,  Shinji Ozaki ,  Shigeyuki Itoh ,  Hikaru Masui ,  Yoshizumi Watatani

发明人： Keiichi Komatsu ,  Shinji Ozaki ,  Shigeyuki Itoh ,  Hikaru Masui ,  Yoshizumi Watatani

IPC分类号： H04N5/91 ,  G11B5/027 ,  G11B27/032 ,  H04N5/265 ,  H04N5/782 ,  H04N9/793 ,  H04N9/80

CPC分类号： H04N5/2621 ,  G11B27/032 ,  H04N5/265 ,  H04N5/782 ,  H04N9/793 ,  H04N9/80

摘要： A pair of recording heads are mounted on a rotary cylinder for recording a video signal in slanted tracks on magnetic tape. The recording heads are mounted in a common plane and each has a different azimuthal angle. A pair of reading heads are mounted on the same rotary cylinder for reading the video signal recorded on the magnetic tape. The reading heads are mounted in a plane offset from the plane of the recording heads and have azimuthal angles that match the azimuthal angles of the recording heads. A mixing circuit mixes a component of the video signal ready from the magnetic tape by one of the recording heads with a video signal from a video signal source to generate a mixed video signal. The mixed video signal is returned to one of the recording heads for recordation on the magnetic tape.

摘要翻译： 一对记录头安装在用于在磁带上的倾斜轨迹中记录视频信号的旋转圆筒上。 记录头安装在公共平面中，每个具有不同的方位角。 一对读取头安装在相同的旋转圆筒上，用于读取记录在磁带上的视频信号。 读取头安装在与记录头的平面偏移的平面中，并且具有与记录头的方位角匹配的方位角。 混合电路通过一个记录头将来自磁带的视频信号的分量与来自视频信号源的视频信号混合，以产生混合视频信号。 混合视频信号返回到一个记录头，用于在磁带上记录。

公开(公告)号：US07594131B2

公开(公告)日：2009-09-22

申请号：US11200193

申请日：2005-08-10

申请人： Shinji Ozaki

发明人： Shinji Ozaki

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F9/3802 ,  G06F1/3203 ,  G06F1/3275 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3869 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13 ,  Y02D10/14

摘要： The processing apparatus in the present invention is a processing apparatus which executes a program and performs processes of the program, and includes the following: an execution circuit having a plurality of operation modes, each of which has a different effect on the processing performance and the power consumption of the processing apparatus; a measurement unit operable to measure at least one of a process execution performance and an execution power consumption of the processor circuit; and a control unit operable to compare a target value and a measurement result from the measurement unit, and to switch the operation modes in accordance to a result of the comparison.

摘要翻译： 本发明的处理装置是执行程序并进行程序处理的处理装置，其特征在于：具有多个操作模式的执行电路，每个操作模式对处理性能和/ 处理装置的功耗; 测量单元，其可操作以测量处理器电路的处理执行性能和执行功耗中的至少一个; 以及控制单元，用于比较来自测量单元的目标值和测量结果，并且根据比较结果切换操作模式。

公开(公告)号：US20070088896A1

公开(公告)日：2007-04-19

申请号：US11510670

申请日：2006-08-28

申请人： Masahide Kakeda ,  Masaitsu Nakajima ,  Takao Yamamoto ,  Shinji Ozaki

发明人： Masahide Kakeda ,  Masaitsu Nakajima ,  Takao Yamamoto ,  Shinji Ozaki

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0893 ,  G06F12/0831

摘要： A cache access transmission means outputs an access address, obtained from a CPU by way of a local cache access address input means, to a shared address bus via a remote cache access address output means. A cache access control means accesses a cache memory by using the access address obtained from the shared address bus by way of a remote cache access address input means. That is, an access address output from a CPU of a first processor is output from the cache access transmission means and received by the cache access control means so as to be used in accessing a cache memory in a second processor.

摘要翻译： 高速缓存存取传输装置经由远程高速缓存存取地址输出装置将通过本地高速缓存存取地址输入装置从CPU获得的访问地址输出到共享地址总线。 高速缓存访​​问控制装置通过使用通过远程高速缓存访​​问地址输入装置从共享地址总线获得的访问地址来访问高速缓冲存储器。 也就是说，从高速缓存访​​问传输装置输出从第一处理器的CPU输出的访问地址，并由高速缓存访​​问控制装置接收，以便用于访问第二处理器中的高速缓冲存储器。

公开(公告)号：US06425047B1

公开(公告)日：2002-07-23

申请号：US09602180

申请日：2000-06-22

申请人： Shinji Ozaki

发明人： Shinji Ozaki

IPC分类号： G06F1300

CPC分类号： G06F13/4239

摘要： A processor that accesses a plurality of regions allocated to memory includes: a judging unit for judging which region is accessed based on an access address; an assuming unit for assuming which region is accessed based on the access address, the assuming unit producing an assumption result faster than the judging unit produces a judgement result; an accessing unit for starting access based on the assumption result; a detecting unit for detecting a disagreement between the judgement result and the assumption result; and a control unit for stopping the access that has been started if the detecting unit has detected the disagreement, and controlling the accessing unit to perform another access based on the judgement result.

摘要翻译： 访问分配给存储器的多个区域的处理器包括：判断单元，用于基于访问地址来判断哪个区域被访问; 假定单元，用于基于所述访问地址来假设哪个区域被访问，所述假设单元产生比所述判断单元更快的假设结果产生判断结果; 基于假设结果开始访问的访问单元; 检测单元，用于检测判断结果与假设结果之间的不一致; 以及控制单元，用于如果检测单元检测到不一致则停止已经开始的访问，并且基于判断结果控制访问单元执行另一访问。

公开(公告)号：US6161171A

公开(公告)日：2000-12-12

申请号：US105212

申请日：1998-06-26

申请人： Toru Morikawa ,  Nobuo Higaki ,  Shinji Ozaki ,  Keisuke Kaneko ,  Satoshi Ogura ,  Masato Suzuki

发明人： Toru Morikawa ,  Nobuo Higaki ,  Shinji Ozaki ,  Keisuke Kaneko ,  Satoshi Ogura ,  Masato Suzuki

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F9/3867 ,  G06F12/0855

摘要： A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.

摘要翻译： 需要从数据存储器中读取数据字并将其存储在寄存器组中的特定寄存器中的第一条指令，然后需要分别从寄存器读出的两个操作数和寄存器中的另一个寄存器的第二条指令 设置，应加入管道处理。 在提供具有较高频率的操作时钟的高速模式中，控制指令执行电路和数据存储器之间的数据高速缓冲存储器，以将数据字提供给指令执行的WB（回写）级 电路相对于与第一指令相关联的输入地址在两个周期内。 为了执行第二指令，数据字从WB级提供给指令执行电路的EX（操作执行）级。 在提供具有较低频率的操作时钟的低速模式中，控制数据高速缓冲存储器以相对于输入地址的一个周期内将数据字提供给指令执行电路的MEM（存储器访问）级 与第一条指令相关联。 为了执行第二条指令，将数据字从MEM级旁路到EX级。

公开(公告)号：US5933465A

公开(公告)日：1999-08-03

申请号：US828387

申请日：1997-03-28

申请人： Shinji Ozaki

发明人： Shinji Ozaki

IPC分类号： H04L27/14 ,  H04B7/005 ,  H04B7/26 ,  H04L1/24 ,  H04L25/06 ,  H04L27/20 ,  H03D1/06 ,  H04L1/00

CPC分类号： H04L25/062 ,  H04L1/24 ,  H04L27/20

摘要： In a control signal detection method, a calibration error value is obtained by obtaining the mean value of the received continuous (4.times.n) data, and the calibration error is compensated with respect to the received data by subtracting the obtained calibration error value from the received data, and the correlation value is obtained on the basis of the corrected received data, so that the control signal is detected. Therefore, it is able to compensate the calibration error with ease and to detect the control signal efficiently, with a simple construction.

摘要翻译： 在控制信号检测方法中，通过获得所接收的连续（4×n）数据的平均值来获得校准误差值，并且通过从接收到的数据中减去所获得的校准误差值来相对于接收数据补偿校准误差 ，并且基于校正的接收数据获得相关值，从而检测控制信号。 因此，能够以简单的结构容易地补偿校准误差并有效地检测控制信号。

公开(公告)号：US5130875A

公开(公告)日：1992-07-14

申请号：US551011

申请日：1990-07-11

申请人： Hiroaki Ono ,  Tomomi Okamoto ,  Shinji Ozaki ,  Tsukasa Ohata

发明人： Hiroaki Ono ,  Tomomi Okamoto ,  Shinji Ozaki ,  Tsukasa Ohata

IPC分类号： G11B5/265 ,  G11B5/53

CPC分类号： G11B5/53 ,  G11B5/531

摘要： In a multichannel magnetic head including a plurality of head chips secured at fixed intervals to one head base mounted on a rotating drum. Each head chip is arranged so that a center of the curvature of each head tip is positioned substantially on a straight line or an extension of the straight line connecting each head gap to tis rear gap, and each of the head chips is arranged so that the distance L between a crossing point on said straight line connecting each head gap to its rear gap and the head gap, and the radius D of the rotating drum satisfy the following relationship: ##EQU1##

摘要翻译： 在包括以固定间隔固定到安装在旋转鼓上的一个头基座的多个头部芯片的多通道磁头中。 每个头部芯片被布置成使得每个头部尖端的曲率的中心基本上位于将每个头部间隙连接到后部间隙的直线或直线的延伸线上，并且每个头部芯片被布置成使得 连接每个头部间隙与其后部间隙的直线上的交叉点与头部间隙之间的距离L以及旋转滚筒的半径D满足以下关系：