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105 条记录 (耗时 0.022 秒)

    Reconfigurable SIMD vector processing system
    11.
    发明授权
    Reconfigurable SIMD vector processing system 有权
    可重构SIMD矢量处理系统

    公开(公告)号：US07519646B2

    公开(公告)日：2009-04-14

    申请号：US11586810

    申请日：2006-10-26

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3828

    摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

    摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

    Dynamic bus repeater with improved noise tolerance
    13.
    发明授权
    Dynamic bus repeater with improved noise tolerance 失效
    具有改善噪声容限的动态总线中继器

    公开(公告)号：US06940313B2

    公开(公告)日：2005-09-06

    申请号：US09895278

    申请日：2001-06-29

    申请人： Mark Anders ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Ram Krishnamurthy

    IPC分类号： G06F13/40 ,  H01L27/108 ,  H03K19/0185 ,  H03K19/096

    CPC分类号： G06F13/4077 ,  H03K19/01855 ,  Y02D10/14 ,  Y02D10/151

    摘要： In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

    摘要翻译： 在一个实施例中，动态总线包括具有约Vcc / 2的噪声容限的动态总线中继器。 总线中继器将总线分为前段和后段。 前段在后段评估时进行预充电，反之亦然。 动态总线中继器在后段被评估时隐藏从后段从前段传播的预充电信号。

    Adder circuit with sense-amplifier multiplexer front-end
    14.
    发明申请
    Adder circuit with sense-amplifier multiplexer front-end 有权
    加法器电路带有读出放大器多路复用器前端

    公开(公告)号：US20050125481A1

    公开(公告)日：2005-06-09

    申请号：US10728127

    申请日：2003-12-04

    申请人： Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy ,  Sapumal Wijeratne

    发明人： Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy ,  Sapumal Wijeratne

    IPC分类号： G06F7/50 ,  G06F7/506 ,  G06F7/507

    CPC分类号： G06F7/507 ,  G06F7/506

    摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.

    摘要翻译： 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。

    Voltage-level converter
    16.
    发明申请
    Voltage-level converter 有权

    公开(公告)号：US20060186924A1

    公开(公告)日：2006-08-24

    申请号：US11411647

    申请日：2006-04-26

    申请人： Steven Hsu ,  Mark Anders ,  Ram Krishnamurthy

    发明人： Steven Hsu ,  Mark Anders ,  Ram Krishnamurthy

    IPC分类号： H03K19/0175

    CPC分类号： H03K3/356113 ,  H03K3/012

    摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

    Low-swing bus driver and receiver
    17.
    发明申请
    Low-swing bus driver and receiver 有权
    低调总线驱动和接收器

    公开(公告)号：US20050148102A1

    公开(公告)日：2005-07-07

    申请号：US10748833

    申请日：2003-12-30

    申请人： Mark Anders ,  Peter Caputa ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Peter Caputa ,  Ram Krishnamurthy

    IPC分类号： H01L21/00

    CPC分类号： H03K19/018521 ,  H03K3/356139 ,  H04L25/028 ,  H04L25/0292

    摘要： According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.

    摘要翻译： 根据一些实施例，提供了一种用于接收全摆幅输入信号，将全摆幅输入信号转换为低摆幅信号并传输低回转信号的静态低摆幅驱动器电路，以及动态 接收器电路来接收低摆动信号并将低摆幅信号转换成全摆幅信号。 还可以提供耦合到驱动器电路和接收器电路的互连，互连不包括中继器并且接收来自驱动器电路的低摆动信号并且将低回转信号发送到接收器电路。

    Transition encoded dynamic bus circuit
    18.
    发明授权
    Transition encoded dynamic bus circuit 有权
    转换编码动态总线电路

    公开(公告)号：US07161992B2

    公开(公告)日：2007-01-09

    申请号：US10035574

    申请日：2001-10-18

    申请人： Mark Anders ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Ram Krishnamurthy

    IPC分类号： H03K9/00

    CPC分类号： H04L25/493 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/14

    摘要： A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. The decoder circuit decodes the transition encoded information to track the appropriate value to be output from the bus.

    摘要翻译： 转换编码的动态总线包括总线输入端的编码器电路和总线输出端的解码器电路。 编码器电路产生指示在总线的输入处的转变而不是输入端的实际值的信号。 解码器电路解码转换编码信息以跟踪从总线输出的适当值。

    Data converter and a delay threshold comparator
    19.
    发明申请
    Data converter and a delay threshold comparator 失效
    数据转换器和延迟阈值比较器

    公开(公告)号：US20060221724A1

    公开(公告)日：2006-10-05

    申请号：US11094811

    申请日：2005-03-31

    申请人： Atul Maheshwari ,  Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy

    发明人： Atul Maheshwari ,  Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy

    IPC分类号： G11C7/06

    CPC分类号： G06F9/3869 ,  G06F7/74

    摘要： For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

    摘要翻译： 对于一个所公开的实施例，转换器将2个N位数据转换为指示具有预定逻辑值的数据中的位数的N位值。 转换器包括N个比较器，每个比较器确定具有预定逻辑值的数据中的位数是否超过多个参考值中的相应一个。 基于比较器的输出产生N位值。 对于另一个公开的实施例，第一延迟元件基于具有预定逻辑值的数据值中的位数来延迟信号，并且第二延迟元件基于具有预定逻辑的参考值中的位数来延迟该信号 值。 比较器然后基于延迟信号产生位值。