中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.018 seconds)

    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT
    1.
    发明申请
    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
    紧凑型低功耗高级加密标准电路

    公开(公告)号：US20150086007A1

    公开(公告)日：2015-03-26

    申请号：US14035508

    申请日：2013-09-24

    Applicant: Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    Inventor： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC: H04L9/30

    CPC classification number: H04L9/0631 ,  H04L2209/24

    Abstract: Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.

    Abstract translation: 公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。 在一个实施例中，装置包括具有替换盒和累加器的加密单元。 替代方案是对每个时钟周期的一个字节执行替换操作。 累加器将累积四个字节，并在四个时钟周期内执行混合列操作。 加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

    Dynamic bus repeater with improved noise tolerance
    4.
    发明授权
    Dynamic bus repeater with improved noise tolerance 失效
    具有改善噪声容限的动态总线中继器

    公开(公告)号：US06940313B2

    公开(公告)日：2005-09-06

    申请号：US09895278

    申请日：2001-06-29

    Applicant: Mark Anders ,  Ram Krishnamurthy

    Inventor： Mark Anders ,  Ram Krishnamurthy

    IPC: G06F13/40 ,  H01L27/108 ,  H03K19/0185 ,  H03K19/096

    CPC classification number: G06F13/4077 ,  H03K19/01855 ,  Y02D10/14 ,  Y02D10/151

    Abstract: In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.

    Abstract translation: 在一个实施例中，动态总线包括具有约Vcc / 2的噪声容限的动态总线中继器。 总线中继器将总线分为前段和后段。 前段在后段评估时进行预充电，反之亦然。 动态总线中继器在后段被评估时隐藏从后段从前段传播的预充电信号。

    Adder circuit with sense-amplifier multiplexer front-end
    5.
    发明申请
    Adder circuit with sense-amplifier multiplexer front-end 有权
    加法器电路带有读出放大器多路复用器前端

    公开(公告)号：US20050125481A1

    公开(公告)日：2005-06-09

    申请号：US10728127

    申请日：2003-12-04

    Applicant: Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy ,  Sapumal Wijeratne

    Inventor： Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy ,  Sapumal Wijeratne

    IPC: G06F7/50 ,  G06F7/506 ,  G06F7/507

    CPC classification number: G06F7/507 ,  G06F7/506

    Abstract: An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.

    Abstract translation: 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。

    Voltage-level converter
    8.
    发明申请
    Voltage-level converter 有权

    公开(公告)号：US20060186924A1

    公开(公告)日：2006-08-24

    申请号：US11411647

    申请日：2006-04-26

    Applicant: Steven Hsu ,  Mark Anders ,  Ram Krishnamurthy

    Inventor： Steven Hsu ,  Mark Anders ,  Ram Krishnamurthy

    IPC: H03K19/0175

    CPC classification number: H03K3/356113 ,  H03K3/012

    Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

    Low-swing bus driver and receiver
    9.
    发明申请
    Low-swing bus driver and receiver 有权
    低调总线驱动和接收器

    公开(公告)号：US20050148102A1

    公开(公告)日：2005-07-07

    申请号：US10748833

    申请日：2003-12-30

    Applicant: Mark Anders ,  Peter Caputa ,  Ram Krishnamurthy

    Inventor： Mark Anders ,  Peter Caputa ,  Ram Krishnamurthy

    IPC: H01L21/00

    CPC classification number: H03K19/018521 ,  H03K3/356139 ,  H04L25/028 ,  H04L25/0292

    Abstract: According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.

    Abstract translation: 根据一些实施例，提供了一种用于接收全摆幅输入信号，将全摆幅输入信号转换为低摆幅信号并传输低回转信号的静态低摆幅驱动器电路，以及动态 接收器电路来接收低摆动信号并将低摆幅信号转换成全摆幅信号。 还可以提供耦合到驱动器电路和接收器电路的互连，互连不包括中继器并且接收来自驱动器电路的低摆动信号并且将低回转信号发送到接收器电路。

    Encoder and decoder circuits for dynamic bus
    10.
    发明申请
    Encoder and decoder circuits for dynamic bus 有权
    用于动态总线的编码器和解码器电路

    公开(公告)号：US20050146357A1

    公开(公告)日：2005-07-07

    申请号：US10744084

    申请日：2003-12-24

    Applicant: Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    Inventor： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC: H03K19/0175 ,  H04L25/02

    CPC classification number: H04L25/0278 ,  H04L25/028

    Abstract: A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

    Abstract translation: 提供动态总线架构。 这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。 编码器电路可以接收输入信号并在总线上生成编码信号。 解码器电路可以从总线接收编码信号并产生原始未编码信号。 编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。 此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

Patent Agency Ranking