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11.发明授权公开(公告)号：US08327188B2
公开(公告)日：2012-12-04
申请号：US12618282
申请日：2009-11-13
IPC分类号： G06F11/00
CPC分类号： G06F11/1405
摘要： The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.
摘要翻译： 所描述的实施例提供用于执行指令的处理器（例如，处理器102）。 在执行期间，处理器通过事先执行来自程序代码的受保护部分的指令来启动。 然后处理器在从程序代码的受保护部分事务地执行指令时遇到事务故障条件。 响应于遇到事务故障条件，处理器进入事务侦察模式并且在事务侦察模式中推测地执行后续指令。
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12.发明授权Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency 有权用于使用包括人为寄存器依赖性的指令协调无序处理器执行中的指令执行的方法和结构公开(公告)号：US07650487B2
公开(公告)日：2010-01-19
申请号：US11371143
申请日：2006-03-08
IPC分类号： G06F9/44
CPC分类号： G06F9/30087 , G06F9/30032 , G06F9/3004 , G06F9/3017 , G06F9/3838 , G06F9/3857
摘要： A technique for coordinating execution of instructions in a processor that allows instructions to execute out-of-order includes decoding a particular instruction that is defined in accordance with an instruction set of the processor. A helper sequence of instructions that corresponds to the particular instruction is then introduced into a stream of executable operations. The corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register that is not actually employed as a register source or target for an operation performed by the particular instruction.
摘要翻译： 用于协调处理器中允许指令执行无序的指令的执行的技术包括解码根据处理器的指令集定义的特定指令。 然后将对应于特定指令的辅助指令序列引入到可执行操作流中。 相应的助手序列包括第一人造依赖指令，其对与实际不用作特定指令执行的操作的寄存器源或目标的寄存器进行编码依赖关系。
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13.发明申请公开(公告)号：US20080172549A1
公开(公告)日：2008-07-17
申请号：US11654271
申请日：2007-01-16
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F11/3612
摘要： One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.
摘要翻译： 本发明的一个实施例提供了一种用于对性能分析目的进行推测执行的指令的计数的系统。 在运行期间，系统对通常在正常执行模式下执行的指令进行计数。 接下来，系统进入推测执行模式，其中指令被推测地执行而不被提交到处理器的架构状态。 在推测执行模式期间，如果推测执行失败，系统会以推测式执行指令的计数复位的方式对推测式执行的指令进行计数。
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14.发明授权公开(公告)号：US07257700B2
公开(公告)日：2007-08-14
申请号：US11053382
申请日：2005-02-07
IPC分类号： G06F9/48
CPC分类号： G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode. Upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the system uses the checkpoint to resume execution in the normal-execution mode from the launch-point instruction. In doing so, the system ensures that entries that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for in order to prevent register RAW hazard when resuming execution from the launch-point instruction.
摘要翻译： 本发明的一个实施例提供一种从推测执行模式返回时避免寄存器读写（RAW）危险的系统。 该系统在具有按顺序架构的处理器内操作，其中处理器包括短延迟记分板，其延迟取决于未完成的短延迟指令的指令的发布。 在操作期间，在正常执行模式下执行程序期间，系统以程序顺序发出执行指令。 在发生指令（发射点指令）期间遇到使处理器进入推测执行模式的条件（发射条件）时，系统产生检查点，该检查点随后可用于将程序的执行返回到 启动点指令，并以推测执行模式开始执行。 当遇到导致处理器离开推测执行模式并返回到启动点指令的条件时，系统使用检查点从启动点指令以正常执行模式恢复执行。 在这样做时，系统确保在进入投机执行模式之前处于短延迟记分板中的条目，以及尚未解决的条目，以便在从启动时恢复执行时防止寄存器RAW危险， 点指令。
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公开(公告)号：US08688963B2
公开(公告)日：2014-04-01
申请号：US12765744
申请日：2010-04-22
IPC分类号： G06F9/00
CPC分类号： G06F9/3863 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3857
摘要： The embodiments described in the instant application provide a system for generating checkpoints. In the described embodiments, while speculatively executing instructions with one or more checkpoints in use, upon detecting an occurrence of a predetermined operating condition or encountering a predetermined type of instruction, the system is configured to determine whether an additional checkpoint is to be generated by computing a factor based on one or more operating conditions of the processor. When the factor is greater than a predetermined value, the processor is configured to generate the additional checkpoint.
摘要翻译： 本申请中描述的实施例提供了一种用于生成检查点的系统。 在所描述的实施例中，当在使用中具有一个或多个检查点的推测执行指令时，在检测到预定操作条件的发生或遇到预定类型的指令时，该系统被配置为确定是否通过计算生成附加检查点 基于处理器的一个或多个操作条件的因素。 当因子大于预定值时，处理器被配置为生成附加检查点。
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公开(公告)号：US20110264898A1
公开(公告)日：2011-10-27
申请号：US12765744
申请日：2010-04-22
CPC分类号： G06F9/3863 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3857
摘要： The embodiments described in the instant application provide a system for generating checkpoints. In the described embodiments, while speculatively executing instructions with one or more checkpoints in use, upon detecting an occurrence of a predetermined operating condition or encountering a predetermined type of instruction, the system is configured to determine whether an additional checkpoint is to be generated by computing a factor based on one or more operating conditions of the processor. When the factor is greater than a predetermined value, the processor is configured to generate the additional checkpoint.
摘要翻译： 本申请中描述的实施例提供了一种用于生成检查点的系统。 在所描述的实施例中，当在使用中具有一个或多个检查点的推测执行指令时，在检测到预定操作条件的发生或遇到预定类型的指令时，该系统被配置为确定是否通过计算生成附加检查点 基于处理器的一个或多个操作条件的因素。 当因子大于预定值时，处理器被配置为生成附加检查点。
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17.发明申请公开(公告)号：US20110119528A1
公开(公告)日：2011-05-19
申请号：US12618282
申请日：2009-11-13
CPC分类号： G06F11/1405
摘要： The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.
摘要翻译： 所描述的实施例提供用于执行指令的处理器（例如，处理器102）。 在执行期间，处理器通过事先执行来自程序代码的受保护部分的指令来启动。 然后处理器在从程序代码的受保护部分事务地执行指令时遇到事务故障条件。 响应于遇到事务故障条件，处理器进入事务侦察模式并且在事务侦察模式中推测地执行后续指令。
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18.发明授权公开(公告)号：US07716457B2
公开(公告)日：2010-05-11
申请号：US11654271
申请日：2007-01-16
IPC分类号： G06F9/00
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F11/3612
摘要： One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.
摘要翻译： 本发明的一个实施例提供了一种用于对性能分析目的进行推测执行的指令的计数的系统。 在运行期间，系统对通常在正常执行模式下执行的指令进行计数。 接下来，系统进入推测执行模式，其中指令被推测地执行而不被提交到处理器的架构状态。 在推测执行模式期间，如果推测执行失败，系统会以推测式执行指令的计数复位的方式对推测式执行的指令进行计数。
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19.发明授权公开(公告)号：US07634639B2
公开(公告)日：2009-12-15
申请号：US11210557
申请日：2005-08-23
申请人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip , Guarav Garg , Ketaki Rao
发明人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip , Guarav Garg , Ketaki Rao
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3863 , G06F9/3885
摘要： One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode, the system checks status indicators associated with a forward progress buffer. If the status indicators indicate that the forward progress buffer contains data for the launch instruction, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators. The system then continues to issue instructions for execution in program order in normal-execution mode. Using the forward progress buffer in this way prevents the processor from entering a potential live-lock state.
摘要翻译： 本发明的一个实施例提供一种避免在支持推测执行的处理器中的实时锁定状态的系统。 系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。 在执行使处理器进入推测执行模式的指令（“启动指令”）期间遇到启动条件时，系统检查与前进进程缓冲器相关联的状态指示符。 如果状态指示灯指示前进进度缓冲区包含启动指令的数据，系统将恢复正常执行模式。 在恢复正常执行模式时，系统从包含在前进进程缓冲器中的数据字段检索数据，并使用检索到的数据作为启动指令的输入数据执行启动指令。 系统接下来取消状态指示。 然后，系统在正常执行模式下继续发出以程序顺序执行的指令。 以这种方式使用前进进程缓冲区可以防止处理器进入潜在的实时锁定状态。
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20.发明授权Method and apparatus for reporting failure conditions during transactional execution 有权在事务执行期间报告故障条件的方法和装置公开(公告)号：US07617421B2
公开(公告)日：2009-11-10
申请号：US11495452
申请日：2006-07-27
IPC分类号： G06F11/00
CPC分类号： G06F11/1407 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3857 , G06F9/467 , G06F11/0724 , G06F11/079
摘要： One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution, and resumes normal non-transactional execution of the program past the block of instructions. Otherwise, if transactional execution of the block of instructions fails, the system discards changes made during the transactional execution, and records failure information indicating why the transactional execution failed.
摘要翻译： 本发明的一个实施例提供一种在事务执行期间报告故障原因的系统。 在操作期间，系统在程序中事务地执行指令块。 如果指令块的事务执行成功完成，则系统将在事务执行期间进行更改，并通过指令块恢复程序的正常非事务性执行。 否则，如果指令块的事务执行失败，则系统将丢弃在事务执行期间所做的更改，并记录指示事务执行失败的原因的故障信息。
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