-
1.发明授权公开(公告)号：US07757068B2
公开(公告)日：2010-07-13
申请号：US11654270
申请日：2007-01-16
IPC分类号： G06F7/38
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06F9/3863 , G06F11/3409 , G06F11/3471 , G06F11/3476 , G06F11/348 , G06F2201/88 , G06F2201/885
摘要： One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the speculative-execution episode the system enables a speculative execution monitor. The system then uses the speculative execution monitor to monitor instructions during the speculative-execution episode to record data values relating to the speculative-execution episode. Upon returning to normal-execution mode, the system disables the speculative execution monitor. The data values recorded by the speculative execution monitor facilitate measuring processor performance during speculative execution.
摘要翻译： 本发明的一个实施例提供了一种用于在推测执行期间测量处理器性能的系统。 系统通过在正常执行模式下执行指令来启动。 然后，系统进入推测执行情节，其中指令被推测地执行而不被提交到处理器的架构状态。 在进入推测执行情节时，系统启用推测执行监视器。 然后，系统使用推测执行监视器在推测执行情节期间监视指令，以记录与推测执行情节相关的数据值。 返回到正常执行模式后，系统将禁用推测执行监视器。 由推测执行监视器记录的数据值有助于在推测执行期间测量处理器的性能。
-
2.发明授权Mechanism for hardware tracking of return address after tail call elimination of return-type instruction 有权尾部呼叫消除返回类型指令后返回地址的硬件跟踪机制公开(公告)号：US07610474B2
公开(公告)日：2009-10-27
申请号：US11352147
申请日：2006-02-10
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3842 , G06F9/3861
摘要： A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one embodiment of the invention, an apparatus includes a processor pipeline and at least a first return address stack for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline. The processor pipeline is configured to maintain the first return address stack unchanged in response to detection of a tail-call elimination sequence of one or more instructions associated with a first call-type instruction encountered by the first stage. The processor pipeline is configured to push a return address associated with the first call-type instruction onto the first return address stack otherwise.
摘要翻译： 检测到返回类型指令的尾部消除消息后，技术维护返回地址堆栈（RAS）内容和RAS顶层（TOS）指针的对齐。 在本发明的至少一个实施例中，一种装置包括处理器流水线和至少第一返回地址堆栈，用于在处理器流水线的第一级保持与指令流相关联的返回地址堆栈。 响应于检测到与第一级遇到的第一呼叫类型指令相关联的一个或多个指令的尾部呼叫消除序列，处理器流水线被配置为维持第一返回地址堆栈不变。 否则处理器流水线被配置为将与第一调用类型指令相关联的返回地址推送到第一返回地址堆栈。
-
3.发明授权Circuitry and method for accessing an associative cache with parallel determination of data and data availability 有权用于通过并行确定数据和数据可用性访问关联高速缓存的电路和方法公开(公告)号：US07461208B1
公开(公告)日：2008-12-02
申请号：US11155147
申请日：2005-06-16
IPC分类号： G06F13/16
CPC分类号： G06F12/0864 , G06F2212/1016 , G06F2212/6082
摘要： A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict. The circuit further includes a memory in communication with the data selection circuitry and the outcome parallel processing circuit. The memory is configured to store a bank select table, whereby the bank select table is configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data. Methods for accessing the associative cache are also described.
摘要翻译： 提供了一种用于访问关联高速缓存的电路。 电路包括与关联高速缓存通信的数据选择电路和结果并行处理电路。 结果并行处理电路被配置为确定来自关联高速缓存的数据的访问是否是高速缓存命中，高速缓存未命中或高速缓存错误预测中的一个。 电路还包括与数据选择电路和结果并行处理电路通信的存储器。 存储器被配置为存储存储体选择表，由此存储体选择表被配置为包括定义从其输出数据的关联高速缓存的多个存储区之一的选择的条目。 还描述了访问关联高速缓存的方法。
-
公开(公告)号：US08364900B2
公开(公告)日：2013-01-29
申请号：US12029889
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/125 , G06F12/0864 , Y02D10/13
摘要： Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate indices using the two or more indices. The system then uses at least one of the two or more indices or the two or more intermediate indices to perform a lookup in one or more lookup tables, wherein the lookup returns a value which identifies a least-recently-used way. Next, the system replaces the entry in the least-recently-used way.
摘要翻译： 本发明的实施例提供了一种在偏斜相关高速缓存中以最近最近使用的方式替换条目的系统。 系统从接收缓存行地址开始。 然后系统使用高速缓存行地址生成两个或多个索引。 接下来，系统使用两个或更多个索引生成两个或更多个中间索引。 然后，系统使用两个或更多个索引中的至少一个或两个或更多个中间索引来在一个或多个查找表中执行查找，其中查找返回标识最近最近使用的方式的值。 接下来，系统以最近最少使用的方式替换条目。
-
5.发明授权Method and apparatus for sampling instructions on a processor that supports speculative execution 有权用于在支持推测性执行的处理器上对指令进行采样的方法和装置公开(公告)号：US07418581B2
公开(公告)日：2008-08-26
申请号：US11405965
申请日：2006-04-17
IPC分类号： G06F9/30
CPC分类号： G06F11/3466 , G06F9/3842 , G06F9/3867
摘要： One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds deferred instructions which are deferred because of an unresolved data dependency. The system then records information about the selected instruction during execution of the selected instruction, whereby the recorded information can be used to determine the performance of the processor.
摘要翻译： 本发明的一个实施例提供了一种在支持推测执行的处理器上对指令进行采样的系统。 系统首先选择指令，其中选择指令涉及选择从指令获取单元或延迟队列接收的指令，其中延迟队列保存由于未解决的数据依赖性而延迟的延迟指令。 然后，系统在执行所选择的指令期间记录关于所选指令的信息，由此可以使用所记录的信息来确定处理器的性能。
-
6.发明授权Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency 有权用于使用包括人为寄存器依赖性的指令协调无序处理器执行中的指令执行的方法和结构公开(公告)号：US07650487B2
公开(公告)日：2010-01-19
申请号：US11371143
申请日：2006-03-08
IPC分类号： G06F9/44
CPC分类号： G06F9/30087 , G06F9/30032 , G06F9/3004 , G06F9/3017 , G06F9/3838 , G06F9/3857
摘要： A technique for coordinating execution of instructions in a processor that allows instructions to execute out-of-order includes decoding a particular instruction that is defined in accordance with an instruction set of the processor. A helper sequence of instructions that corresponds to the particular instruction is then introduced into a stream of executable operations. The corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register that is not actually employed as a register source or target for an operation performed by the particular instruction.
摘要翻译： 用于协调处理器中允许指令执行无序的指令的执行的技术包括解码根据处理器的指令集定义的特定指令。 然后将对应于特定指令的辅助指令序列引入到可执行操作流中。 相应的助手序列包括第一人造依赖指令，其对与实际不用作特定指令执行的操作的寄存器源或目标的寄存器进行编码依赖关系。
-
7.发明申请公开(公告)号：US20080172549A1
公开(公告)日：2008-07-17
申请号：US11654271
申请日：2007-01-16
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F11/3612
摘要： One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.
摘要翻译： 本发明的一个实施例提供了一种用于对性能分析目的进行推测执行的指令的计数的系统。 在运行期间，系统对通常在正常执行模式下执行的指令进行计数。 接下来，系统进入推测执行模式，其中指令被推测地执行而不被提交到处理器的架构状态。 在推测执行模式期间，如果推测执行失败，系统会以推测式执行指令的计数复位的方式对推测式执行的指令进行计数。
-
8.发明授权公开(公告)号：US07257700B2
公开(公告)日：2007-08-14
申请号：US11053382
申请日：2005-02-07
IPC分类号： G06F9/48
CPC分类号： G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode. Upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the system uses the checkpoint to resume execution in the normal-execution mode from the launch-point instruction. In doing so, the system ensures that entries that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for in order to prevent register RAW hazard when resuming execution from the launch-point instruction.
摘要翻译： 本发明的一个实施例提供一种从推测执行模式返回时避免寄存器读写（RAW）危险的系统。 该系统在具有按顺序架构的处理器内操作，其中处理器包括短延迟记分板，其延迟取决于未完成的短延迟指令的指令的发布。 在操作期间，在正常执行模式下执行程序期间，系统以程序顺序发出执行指令。 在发生指令（发射点指令）期间遇到使处理器进入推测执行模式的条件（发射条件）时，系统产生检查点，该检查点随后可用于将程序的执行返回到 启动点指令，并以推测执行模式开始执行。 当遇到导致处理器离开推测执行模式并返回到启动点指令的条件时，系统使用检查点从启动点指令以正常执行模式恢复执行。 在这样做时，系统确保在进入投机执行模式之前处于短延迟记分板中的条目，以及尚未解决的条目，以便在从启动时恢复执行时防止寄存器RAW危险， 点指令。
-
9.发明授权公开(公告)号：US07716457B2
公开(公告)日：2010-05-11
申请号：US11654271
申请日：2007-01-16
IPC分类号： G06F9/00
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F11/3612
摘要： One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.
摘要翻译： 本发明的一个实施例提供了一种用于对性能分析目的进行推测执行的指令的计数的系统。 在运行期间，系统对通常在正常执行模式下执行的指令进行计数。 接下来，系统进入推测执行模式，其中指令被推测地执行而不被提交到处理器的架构状态。 在推测执行模式期间，如果推测执行失败，系统会以推测式执行指令的计数复位的方式对推测式执行的指令进行计数。
-
10.发明授权公开(公告)号：US07634639B2
公开(公告)日：2009-12-15
申请号：US11210557
申请日：2005-08-23
申请人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip , Guarav Garg , Ketaki Rao
发明人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip , Guarav Garg , Ketaki Rao
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F9/3863 , G06F9/3885
摘要： One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode, the system checks status indicators associated with a forward progress buffer. If the status indicators indicate that the forward progress buffer contains data for the launch instruction, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators. The system then continues to issue instructions for execution in program order in normal-execution mode. Using the forward progress buffer in this way prevents the processor from entering a potential live-lock state.
摘要翻译： 本发明的一个实施例提供一种避免在支持推测执行的处理器中的实时锁定状态的系统。 系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。 在执行使处理器进入推测执行模式的指令（“启动指令”）期间遇到启动条件时，系统检查与前进进程缓冲器相关联的状态指示符。 如果状态指示灯指示前进进度缓冲区包含启动指令的数据，系统将恢复正常执行模式。 在恢复正常执行模式时，系统从包含在前进进程缓冲器中的数据字段检索数据，并使用检索到的数据作为启动指令的输入数据执行启动指令。 系统接下来取消状态指示。 然后，系统在正常执行模式下继续发出以程序顺序执行的指令。 以这种方式使用前进进程缓冲区可以防止处理器进入潜在的实时锁定状态。
-
-
-
-
-
-
-
-
-
搜索结果
219 条记录 (耗时 0.024 秒)
