公开(公告)号：US06339387B1

公开(公告)日：2002-01-15

申请号：US09583232

申请日：2000-05-31

申请人： Makoto Koga

发明人： Makoto Koga

IPC分类号： H03M900

CPC分类号： H03M9/00

摘要： According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

公开(公告)号：US6119150A

公开(公告)日：2000-09-12

申请号：US789184

申请日：1997-01-24

申请人： Hiroaki Fujii ,  Tadaaki Isobe ,  Makoto Koga ,  Hideya Akashi

发明人： Hiroaki Fujii ,  Tadaaki Isobe ,  Makoto Koga ,  Hideya Akashi

IPC分类号： G06F15/17 ,  G06F12/08 ,  G06F15/167 ,  G06F13/00

CPC分类号： G06F12/0837 ,  G06F12/0813

摘要： An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

摘要翻译： 采用根据来自存储控制器的请求执行高速缓存一致性控制的指令处理器。 存储控制器设置有高速缓存一致性控制处理电路，其对作为通过数据传送发生的主存储器访问的目的地的地址执行高速缓存一致性控制。 同时，高速缓存一致性控制处理电路在数据传送过程中对每条高速缓存线执行一次高速缓存一致性控制处理。 消除了与数据传输有关的软件执行的高速缓存一致性控制处理，提高了包括缓存存储器控制在内的数据传输效率，并减少了对程序的限制。

公开(公告)号：US07639038B2

公开(公告)日：2009-12-29

申请号：US11485396

申请日：2006-07-13

申请人： Yutaka Nemoto ,  Yoshimasa Ogawa ,  Miki Yanagawa ,  Makoto Koga

发明人： Yutaka Nemoto ,  Yoshimasa Ogawa ,  Miki Yanagawa ,  Makoto Koga

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0298

摘要： A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit. The method includes obtaining a comparison result by comparing a reference voltage and a voltage of a first node that is coupled to a first voltage via a current supply circuit, the first voltage being one of a power supply voltage and a ground voltage, controlling a monitoring resistor part which has a plurality of first resistors when making a calibration, so as to selectively couple the first resistors in parallel between the first node and a second voltage based on the comparison result, the second voltage being the other of the power supply voltage and the ground voltage, and controlling a terminating resistor part which has a plurality of second resistors when controlling the terminating resistance of the terminating part, so as to selectively couple the second resistors in parallel between a second node and the second voltage based on the comparison result similarly to the first resistors of the monitoring resistor part.

摘要翻译： 终端电阻调整方法调整半导体集成电路内的终端电阻。 该方法包括通过比较经由电流供应电路耦合到第一电压的第一节点的参考电压和电压，第一电压是电源电压和接地电压之一来获得比较结果，控制监视 电阻部分，当进行校准时具有多个第一电阻器，以便基于比较结果选择性地将第一电阻并联在第一节点和第二电压之间，第二电压是电源电压的另一个， 接地电压，并且当控制终端部分的终止电阻时控制具有多个第二电阻器的终端电阻器部分，以便基于比较结果选择性地将第二电阻并联连接在第二节点和第二电压之间 类似于监控电阻器部分的第一个电阻。

公开(公告)号：US06740929B2

公开(公告)日：2004-05-25

申请号：US10320420

申请日：2002-12-17

申请人： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

发明人： Makoto Koga ,  Kunihiko Gotoh ,  Kenichi Matsumaru ,  Mitsuya Kawata

IPC分类号： H01L2900

CPC分类号： G11C29/26 ,  G11C8/12

摘要： A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

摘要翻译： 具有至少三个可独立存取存储器的半导体器件，其中至少一个存储器具有与其它存储器不同的存储器容量。 将独立的选择信号提供给存储器，使得它们可以被独立地激活。 这允许记忆分开测试。 当测试半导体器件时，除了具有最大容量的存储器之外，连续测试存储器，因为该存储器也具有最长的测试时间。 具有最长测试时间的存储器与串行测试的存储器并行测试。 这在测试期间将测试装置必须提供的电流减少到半导体器件。

公开(公告)号：US20070216441A1

公开(公告)日：2007-09-20

申请号：US11485396

申请日：2006-07-13

申请人： Yutaka Nemoto ,  Yoshimasa Ogawa ,  Miki Yanagawa ,  Makoto Koga

发明人： Yutaka Nemoto ,  Yoshimasa Ogawa ,  Miki Yanagawa ,  Makoto Koga

IPC分类号： H03K19/003

CPC分类号： H04L25/0298

摘要： A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit. The method includes obtaining a comparison result by comparing a reference voltage and a voltage of a first node that is coupled to a first voltage via a current supply circuit, the first voltage being one of a power supply voltage and a ground voltage, controlling a monitoring resistor part which has a plurality of first resistors when making a calibration, so as to selectively couple the first resistors in parallel between the first node and a second voltage based on the comparison result, the second voltage being the other of the power supply voltage and the ground voltage, and controlling a terminating resistor part which has a plurality of second resistors when controlling the terminating resistance of the terminating part, so as to selectively couple the second resistors in parallel between a second node and the second voltage based on the comparison result similarly to the first resistors of the monitoring resistor part.

摘要翻译： 终端电阻调整方法调整半导体集成电路内的终端电阻。 该方法包括通过比较经由电流供应电路耦合到第一电压的第一节点的参考电压和电压，第一电压是电源电压和接地电压之一来获得比较结果，控制监视 电阻部分，当进行校准时具有多个第一电阻器，以便基于比较结果选择性地将第一电阻并联在第一节点和第二电压之间，第二电压是电源电压的另一个， 接地电压，并且当控制终端部分的终止电阻时控制具有多个第二电阻器的终端电阻器部分，以便基于比较结果选择性地将第二电阻并联连接在第二节点和第二电压之间 类似于监控电阻器部分的第一个电阻。

公开(公告)号：US6097323A

公开(公告)日：2000-08-01

申请号：US63790

申请日：1998-04-22

申请人： Makoto Koga ,  Yoshinori Okajima

发明人： Makoto Koga ,  Yoshinori Okajima

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

摘要翻译： 根据本发明，串行/并行转换器以相同相位并行地输出与输入时钟同步串行输入的多个数据组，包括：至少两个输入锁存触发器，用于锁存 多个输入数据组与输入时钟同步; 脉冲发生器，用于与所述多个数据组由所述输入锁存触发器保持的定时同步地产生多个锁存时钟; 多个保持翻转开关，用于根据所述多个锁存时钟按顺序由所述输入锁存触发器保持的所述多个数据组进行锁存; 以及多个输出锁存触发器，用于当与输入锁存触发器保持多个数据组的最后一个数据组时同步的最后一个锁存时钟，并行地锁存多个保持的数据集 通过保持触发器和由输入锁存器触发器设置的最后数据。

公开(公告)号：US5838604A

公开(公告)日：1998-11-17

申请号：US803448

申请日：1997-02-20

申请人： Hironobu Tsuboi ,  Yoshinori Okajima ,  Tsuyoshi Higuchi ,  Makoto Koga

发明人： Hironobu Tsuboi ,  Yoshinori Okajima ,  Tsuyoshi Higuchi ,  Makoto Koga

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C11/409 ,  G11C7/10

摘要： A semiconductor memory device includes a plurality of bit lines, first sense amplifiers each connected to a corresponding one of the plurality of bit lines, and a first data bus laid out in parallel to the plurality of bit lines and connected to the plurality of bit lines via gates and the first sense amplifiers. The semiconductor memory device further includes column-selection lines laid out perpendicularly to the plurality of bit lines to open at least one of the gates to connect the first data bus to the plurality of bit lines.

摘要翻译： 半导体存储器件包括多个位线，每个连接到多个位线中的相应一个位线的第一读出放大器和与多个位线并联布置并连接到多个位线的第一数据总线 通过门和第一感测放大器。 半导体存储器件还包括垂直于多个位线布置的列选择线，以打开至少一个栅极，以将第一数据总线连接到多个位线。