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公开(公告)号：US20060114708A1
公开(公告)日：2006-06-01
申请号：US11272818
申请日：2005-11-15
IPC分类号： G11C17/00
摘要： Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.
摘要翻译： 从解码器输出的选择信号根据单元组指定电路中的位单元中的状态（发生或不发生）或熔丝选择性地设置为高。 然后，晶体管栅极中的一个导通，从而选择写入/读出数据的数据位单元组。 因此，可以通过在单元组指定电路中顺序吹送保险丝来重写多个存储的数据。
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公开(公告)号：US07050347B2
公开(公告)日：2006-05-23
申请号：US11038025
申请日：2005-01-21
IPC分类号： G11C7/02
CPC分类号： G11C29/50 , G11C2029/1204 , G11C2029/5004
摘要： In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.
摘要翻译： 在正常操作中，输出用于放大第一和第二位单元之间的差分的差分放大器的输出作为读出数据。 在测试模式中，当第一控制信号被设置为“H”时，差分放大器的输出被固定为“H”，从而通过门读出第一位单元的输出。
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公开(公告)号：US20060039209A1
公开(公告)日：2006-02-23
申请号：US11202230
申请日：2005-08-12
IPC分类号： G11C7/00
摘要： Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second resistance elements; a voltage comparing circuit which outputs an output corresponding to the voltage conversion; a latch circuit for holding the output of the voltage comparing circuit; and a switch circuit which cuts and connects the voltage converting circuit and the voltage comparing circuit.
摘要翻译： 提供一种半导体存储器，包括：电压转换电路，其对第一和第二电阻元件之间的电阻差进行电压转换; 电压比较电路，其输出与电压转换相对应的输出; 用于保持电压比较电路的输出的锁存电路; 以及切换并连接电压转换电路和电压比较电路的开关电路。
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公开(公告)号：US20050052926A1
公开(公告)日：2005-03-10
申请号：US10935278
申请日：2004-09-08
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0425
摘要： A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.
摘要翻译： 非易失性半导体存储器件包括：第一位单元，包括其源极和漏极连接以形成第一控制栅极的第一MOS晶体管和具有与第一MOS晶体管共同的浮动栅极的第二MOS晶体管; 第二位单元，包括其源极和漏极连接以形成第二控制栅极的第三MOS晶体管和具有与第三MOS晶体管共同的浮置栅极的第四MOS晶体管; 以及差分放大器，其从相应的第二和第四MOS晶体管的漏极接收输入信号。
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公开(公告)号：US07791973B2
公开(公告)日：2010-09-07
申请号：US12021317
申请日：2008-01-29
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.
摘要翻译： 第一晶体管与保险丝元件的一端串联连接。 第二晶体管与保险丝元件的另一端串联连接。 当第一和第二晶体管都导通时，电流流过熔丝元件。
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公开(公告)号：US07397720B2
公开(公告)日：2008-07-08
申请号：US11501039
申请日：2006-08-09
申请人： Shinichi Sumi , Hirohito Kikukawa , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara , Yasue Yamamoto
发明人： Shinichi Sumi , Hirohito Kikukawa , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara , Yasue Yamamoto
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027 , G11C29/785 , G11C2229/763
摘要： Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.
摘要翻译： 提供多级的电熔丝块（100），每个级包括多个电熔丝芯（101）。 电熔丝块（100）包括由移位寄存器（107）构成的程序移位寄存器块（103），它们被设置用于相应的电熔丝芯（101），顺序发送编程使能信号FPGI，并输出编程使能信号 FPGI连接到电熔丝芯（101）的NMOS晶体管（105）。 当根据编程判定信号PBn执行编程时，程序移位寄存器块（103）发送程序使能信号FPGI。 当不执行编程时，程序移位寄存器块（103）跳过编程使能信号FPGI。
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公开(公告)号：US20070097573A1
公开(公告)日：2007-05-03
申请号：US11526816
申请日：2006-09-26
申请人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H02H3/20
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译： 系统LSI包括输入/输出部分和逻辑电路部分。 输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供 来自I / O电源单元的源电源。 逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。
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公开(公告)号：US07884642B2
公开(公告)日：2011-02-08
申请号：US12722317
申请日：2010-03-11
申请人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H03K19/173
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译： 系统LSI包括输入/输出部分和逻辑电路部分。 输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供 来自I / O电源单元的源电源。 逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。
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公开(公告)号：US07696779B2
公开(公告)日：2010-04-13
申请号：US11526816
申请日：2006-09-26
申请人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H03K19/173
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译： 系统LSI包括输入/输出部分和逻辑电路部分。 输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供 来自I / O电源单元的源电源。 逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。
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公开(公告)号：US20070058411A1
公开(公告)日：2007-03-15
申请号：US11501039
申请日：2006-08-09
申请人： Shinichi Sumi , Hirohito Kikukawa , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara , Yasue Yamamoto
发明人： Shinichi Sumi , Hirohito Kikukawa , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara , Yasue Yamamoto
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027 , G11C29/785 , G11C2229/763
摘要： Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.
摘要翻译： 提供多级的电熔丝块（100），每个级包括多个电熔丝芯（101）。 电熔丝块（100）包括由移位寄存器（107）构成的程序移位寄存器块（103），它们被设置用于相应的电熔丝芯（101），顺序发送编程使能信号FPGI，并输出编程使能信号 FPGI连接到电熔丝芯（101）的NMOS晶体管（105）。 当根据编程判定信号PBn执行编程时，程序移位寄存器块（103）发送程序使能信号FPGI。 当不执行编程时，程序移位寄存器块（103）跳过编程使能信号FPGI。
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