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    System and method wherein conditional instructions unconditionally provide output
    12.
    发明授权
    System and method wherein conditional instructions unconditionally provide output 有权
    其中条件指令无条件地提供输出的系统和方法

    公开(公告)号：US07624256B2

    公开(公告)日：2009-11-24

    申请号：US11106803

    申请日：2005-04-14

    申请人： Thomas Andrew Sartorius ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F13/00

    CPC分类号： G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

    摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

    摘要翻译： 一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便 它无条件地向目标提供输出。 条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。 评估条件。 如果满足条件，则执行操作并将操作结果输出到目标。 如果条件不满足，则将先前值输出到目标。 后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

    Power efficient instruction prefetch mechanism
    13.
    发明授权
    Power efficient instruction prefetch mechanism 有权
    高效的指令预取机制

    公开(公告)号：US07587580B2

    公开(公告)日：2009-09-08

    申请号：US11050932

    申请日：2005-02-03

    申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3844 ,  G06F9/3804

    摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

    摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

    Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state
    15.
    发明授权
    Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state 有权
    省电方法和装置，用于基于已知的处理器状态选择性地启用CAM重命名寄存器文件中的比较器

    公开(公告)号：US07263577B2

    公开(公告)日：2007-08-28

    申请号：US11072849

    申请日：2005-03-03

    申请人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

    发明人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30058 ,  G06F1/3203 ,  G06F1/3275 ,  G06F9/384 ,  Y02D10/13 ,  Y02D10/14

    摘要： A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of physical registers than addressable by direct use of the IRN. The renaming register file uses a content addressable memory (CAM) to provide the mapping function. The renaming register file CAM further uses current processor state information to selectively enable tag comparators to minimize power in accessing registers. When a tag comparator is not enabled it remains in a low power state. A processor using a renaming register file with low power features is also described.

    摘要翻译： 描述了一种用于节省电力的重命名寄存器文件。 映射单元将指令寄存器号（IRN）变换为逻辑寄存器号（LRN）。 重命名寄存器文件将LRN映射到物理寄存器编号（PRN），通过直接使用IRN，存在比可寻址的更大数量的物理寄存器。 重命名寄存器文件使用内容可寻址存储器（CAM）来提供映射功能。 重命名寄存器文件CAM还使用当前处理器状态信息来选择性地使标签比较器最小化访问寄存器的功率。 当标签比较器未使能时，它保持在低功率状态。 还描述了使用具有低功率特征的重命名寄存器文件的处理器。