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    Write-Through-Read (WTR) Comparator Circuits, Systems, and Methods Employing Write-Back Stage and Use of Same With A Multiple-Port File
    5.
    发明申请
    Write-Through-Read (WTR) Comparator Circuits, Systems, and Methods Employing Write-Back Stage and Use of Same With A Multiple-Port File 有权
    直写读取（WTR）比较器电路，系统和采用回写阶段的方法和使用与多端口文件相同

    公开(公告)号：US20110197021A1

    公开(公告)日：2011-08-11

    申请号：US12703342

    申请日：2010-02-10

    申请人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamaker ,  Yeshwant Nagaraj Kolla

    发明人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamaker ,  Yeshwant Nagaraj Kolla

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30141 ,  G06F9/3857

    摘要： Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

    摘要翻译： 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯所需的功耗，成本和面积。

    Digital data processing apparatus having multi-level register file
    6.
    发明授权
    Digital data processing apparatus having multi-level register file 失效
    具有多级寄存器文件的数字数据处理装置

    公开(公告)号：US07284092B2

    公开(公告)日：2007-10-16

    申请号：US10875373

    申请日：2004-06-24

    申请人： Nathan Samuel Nunamaker ,  Jack Chris Randolph ,  Kenichi Tsuchiya

    发明人： Nathan Samuel Nunamaker ,  Jack Chris Randolph ,  Kenichi Tsuchiya

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F9/30138 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3851 ,  G06F9/3861 ,  G06F12/0875

    摘要： A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

    摘要翻译： 处理器包含具有不同访问延迟的多级寄存器。 相对较小的寄存器集合包含在相对较快的较高级别的寄存器组中，并且较大的更完整的寄存器集合包含在相对较慢的较低级别的寄存器组中。 在物理上，较高级别的寄存器组被放置得更接近从寄存器接收输入的功能逻辑。 优选地，下级存储体包括一整套所有处理器寄存器，并且较高级存储体包括较小的寄存器子集，复制下级存储体中的信息。 较高级别的存储体优选在单个时钟周期内可访问。

    Digital data processing apparatus having multi-level register file
    7.
    发明授权
    Digital data processing apparatus having multi-level register file 失效
    具有多级寄存器文件的数字数据处理装置

    公开(公告)号：US08793433B2

    公开(公告)日：2014-07-29

    申请号：US11835519

    申请日：2007-08-08

    申请人： Nathan Samuel Nunamaker ,  Jack Chris Randolph ,  Kenichi Tsuchiya

    发明人： Nathan Samuel Nunamaker ,  Jack Chris Randolph ,  Kenichi Tsuchiya

    IPC分类号： G06F12/02

    CPC分类号： G06F9/30138 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3851 ,  G06F9/3861 ,  G06F12/0875

    摘要： A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Selection logic enables selecting output of either register bank for input to processor execution logic. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

    摘要翻译： 处理器包含具有不同访问延迟的多级寄存器。 相对较小的寄存器集合包含在相对较快的较高级别的寄存器组中，并且较大的更完整的寄存器集合包含在相对较慢的较低级别的寄存器组中。 在物理上，较高级别的寄存器组被放置得更接近从寄存器接收输入的功能逻辑。 选择逻辑使能选择任一寄存器组的输出，以输入到处理器执行逻辑。 优选地，下级存储体包括一整套所有处理器寄存器，并且较高级存储体包括较小的寄存器子集，复制下级存储体中的信息。 较高级别的存储体优选在单个时钟周期内可访问。