公开(公告)号：US20060103425A1

公开(公告)日：2006-05-18

申请号：US11272847

申请日：2005-11-14

申请人： Michele La Placa ,  Ignazio Martines

发明人： Michele La Placa ,  Ignazio Martines

IPC分类号： H03K19/0175

CPC分类号： H03K19/0013

摘要： The output buffer stage includes a half-bridge output stage having a first pair of complementary drivers connected in series between a supply line and a ground node, the high impedance state or conduction state of which is determined through a pair of control phases. The buffer stage includes a pair of switches controlled by the control phases, connected in series between them and connecting the transistors of the first stage in series. Each driver is connected in series with a switch, that is quickly opened to prevent under-threshold currents from circulating when the respective driver is turned off, and that is rapidly turned off when the respective driver is turned on.

摘要翻译： 输出缓冲级包括半桥输出级，其具有串联连接在电源线和接地节点之间的第一对互补驱动器，其高阻抗状态或导通状态通过一对控制相确定。 缓冲级包括由控制相位控制的一对开关，串联连接在一起，并连接第一级的晶体管。 每个驱动器与开关串联连接，快速打开，以防止相应驱动器关闭时低阈值电流循环，并且当相应驱动器打开时快速关闭。

公开(公告)号：US06324098B1

公开(公告)日：2001-11-27

申请号：US09546957

申请日：2000-04-11

申请人： Carmelo Condemi ,  Michele La Placa ,  Ignazio Martines

发明人： Carmelo Condemi ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C1600

CPC分类号： G11C16/28

摘要： A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.

摘要翻译： 一种用于非易失性存储单元的读取电路，包括具有连接到存储单元的阵列负载的电流 - 电压转换器和连接到参考发生器的参考负载。 阵列负载和参考负载包括呈现阵列形状因子（W / L）F和分别为参考形状因子（W / L）R的PMOS晶体管。 读取电路还包括电荷泵，其将偏置电压提供给存储器单元的栅极端子。 偏置电压与电源电压VDD成比例。 阵列形状系数（W / L）F与基准形状系数（W / L）R的比率为非整数。

公开(公告)号：US06243310B1

公开(公告)日：2001-06-05

申请号：US09546975

申请日：2000-04-11

申请人： Carmelo Condemi ,  Michele La Placa ,  Ignazio Martines

发明人： Carmelo Condemi ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C700

CPC分类号： G11C16/28 ,  G11C7/12 ,  G11C16/32

摘要： An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.

摘要翻译： 一种具有均衡信号产生级的均衡控制电路，其具有接收地址转换信号的使能输入，接收禁止信号的禁止输入和产生均衡控制信号的输出。 在一个初始端子（35a）处提供与提供给寻址的阵列单元的读取电压相关的偏置电压的辅助线。 均衡滤波器连接到辅助线路的终端，当辅助线路末端的电压超过预设的阈值时，产生禁用信号。

公开(公告)号：US6097633A

公开(公告)日：2000-08-01

申请号：US182843

申请日：1998-10-29

申请人： Michele La Placa

发明人： Michele La Placa

IPC分类号： G11C7/06 ,  G11C16/28 ,  G11C16/06

CPC分类号： G11C7/062 ,  G11C16/28

摘要： A read circuit for non-volatile memories having an array section, with a corresponding bitline, and a reference section, with a corresponding reference bitline. A differential amplifier for comparing voltage signals obtained by current/voltage conversion of a current signal of an array cell and of a reference current signal is connected to the respective bit lines. A cascode transistor for each one of the array and reference sections, each driven by a NOR logic gate; a charge transistor for the bitline and a charge transistor for the reference bitline; column decoding transistors for the array section and for the reference section; the circuit further comprising an additional transistor which is connected between the NOR gate of the array side and a node for acquiring the array voltage sent to the differential amplifier, the additional transistor increasing the speed of the process for reading the bitline when the bitline is not charged.

摘要翻译： 具有具有相应位线的阵列部分和具有相应参考位线的参考部分的非易失性存储器的读取电路。 用于比较通过阵列单元的电流信号的电流/电压转换获得的电压信号和参考电流信号的差分放大器连接到各个位线。 用于阵列和参考部分中的每一个的共源共栅晶体管，每个由NOR逻辑门驱动; 用于位线的充电晶体管和用于参考位线的充电晶体管; 用于阵列部分和参考部分的列解码晶体管; 该电路还包括连接在阵列侧的或非门之间的附加晶体管和用于获取发送到差分放大器的阵列电压的节点，附加晶体管增加了当位线不是时读取位线的处理速度 带电。

公开(公告)号：US07826284B2

公开(公告)日：2010-11-02

申请号：US11726993

申请日：2007-03-23

申请人： Michele La Placa ,  Ignazio Martines

发明人： Michele La Placa ,  Ignazio Martines

IPC分类号： G11C11/063

CPC分类号： G11C7/067 ,  G11C11/5642 ,  G11C16/28 ,  G11C2207/063

摘要： A sensing circuit for a semiconductor memory, includes, a detecting amplifier including a first circuital branch is run through by a first current corresponding to the sum of a second current as a function of a comparison current and a cell current. The cell current is a function of a state of a memory cell to be read in a predetermined biasing condition. A second circuital branch is coupled as a current mirror configuration with the first circuital branch. The second circuital branch is run through by a third current proportional to the first current. A third circuital branch coupled to the second branch sinks a fourth current as a function of the comparison current. A fourth circuital branch coupled to is run through by a residual current equal to the difference between the third and the fourth current. The residual current assumes different values depending on the fact that the cell current is lower, equal or higher than the comparison current. A residual current sensitive means generates an indication of the state of the memory cell as a function of a value of the residual current.

摘要翻译： 一种用于半导体存储器的感测电路，包括：包括第一电路分支的检测放大器，通过对应于作为比较电流和单元电流的函数的第二电流之和的第一电流运行。 单元电流是在预定的偏置条件下要读取的存储单元的状态的函数。 第二电路分支作为电流镜配置与第一电路分支耦合。 第二电路分支通过与第一电流成比例的第三电流。 耦合到第二分支的第三电路分支作为比较电流的函数吸收第四电流。 耦合的第四电路分支通过等于第三和第四电流之间的差的剩余电流流过。 根据电池电流低于等于或高于比较电流的事实，剩余电流取决于不同的值。 剩余电流敏感装置根据剩余电流的值产生存储器单元的状态的指示。

公开(公告)号：US20080258807A1

公开(公告)日：2008-10-23

申请号：US11455896

申请日：2006-06-19

申请人： Ignazio Martines ,  Michele La Placa

发明人： Ignazio Martines ,  Michele La Placa

IPC分类号： H03H11/00

CPC分类号： G05F3/242

摘要： A basic electronic circuit generates a magnitude. The circuit has certain structural characteristics and the magnitude undergoes variations in function of the structural characteristics of the circuit. The circuit comprises at least two circuit parts suitable for supplying respective fractions of the magnitude and the at least two circuit parts have different structural characteristics.

摘要翻译： 基本的电子电路产生大小。 该电路具有一定的结构特征，并且幅度在电路结构特性的作用上发生变化。 该电路包括至少两个电路部件，适于提供大小的各个部分，并且至少两个电路部件具有不同的结构特征。

公开(公告)号：US07414459B2

公开(公告)日：2008-08-19

申请号：US11444287

申请日：2006-05-31

申请人： Michelangelo Pisasale ,  Vincenzo Sambataro ,  Maurizio Gaibotti ,  Michele La Placa

发明人： Michelangelo Pisasale ,  Vincenzo Sambataro ,  Maurizio Gaibotti ,  Michele La Placa

IPC分类号： H02M3/06

CPC分类号： G11C5/147 ,  G11C16/30

摘要： An architecture for implementing an integrated capacity includes a capacitive block inserted between first and second voltage reference. The block is formed The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block. The verify and enable circuit detects the presence of a current value in each of the elementary capacitive modules and, if said current is detected, disables that elementary capacitive module of the capacitive block using the corresponding switch of the enable block.

摘要翻译： 用于实现集成容量的架构包括插入在第一和第二电压基准之间的电容性块。 该块由基本电容模块形成。 在第一电压基准和电容性块之间插入使能块，并且包括连接到基本电容模块并通过控制信号在其控制端子上驱动的开关。 使能块的每个开关插入在第一参考电压和对应的基本电容模块的第一端之间。 验证和使能电路连接到第一参考电压以及基本电容模块的第一端的输入端以及使能块的开关的控制端子的输出。 验证和使能电路检测每个基本电容模块中是否存在电流值，并且如果检测到所述电流，则使用使能块的相应开关禁用电容块的基本电容模块。

公开(公告)号：US07242619B2

公开(公告)日：2007-07-10

申请号：US11238137

申请日：2005-09-28

申请人： Ignazio Martines ,  Michele La Placa

发明人： Ignazio Martines ,  Michele La Placa

IPC分类号： G11C11/34

CPC分类号： G11C16/28

摘要： Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference voltage, which are compared to determine the contents of the array memory cell. The method envisages reducing the electrical stress to which the reference memory cell is subjected during reading, by generating and holding a sample of the reference voltage, then deselecting the reference memory cell, and then continuing reading using the sample of the reference voltage.

公开(公告)号：US20060245269A1

公开(公告)日：2006-11-02

申请号：US11279663

申请日：2006-04-13

申请人： Ignazio Martines ,  Michele La Placa

发明人： Ignazio Martines ,  Michele La Placa

IPC分类号： G11C7/10

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： A method for simultaneously programming a pre-established number of memory cells includes setting an initial number of memory cells to be simultaneously programmed equal to the pre-established number, and subdividing the initial number of memory cells to be programmed into subsets of memory cells. A program operation for simultaneously programming all the memory cells of each subset of memory cells is executed by forcing a current through all the memory cells of each subset of memory cells. The current has a program voltage associated therewith. The program voltage is compared to a threshold voltage during execution of the program operation. The method further includes stopping execution of the program operation if the threshold voltage is surpassed, reducing the initial number of memory cells to be simultaneously programmed, and restarting from the subdividing.

摘要翻译： 用于同时编程预先建立的数量的存储器单元的方法包括设置要等同于预先建立的数量的同步编程的存储器单元的初始数量，并将待编程的存储器单元的初始数量细分为存储器单元的子集。 通过强制电流通过存储器单元的每个子集的所有存储器单元来执行用于同时编程存储器单元的每个子集的所有存储单元的程序操作。 电流具有与其相关联的编程电压。 在执行程序操作期间将编程电压与阈值电压进行比较。 该方法还包括如果超过阈值电压则停止执行程序操作，减少要同步编程的存储器单元的初始数目，并从再划分重新启动。

公开(公告)号：US20060164888A1

公开(公告)日：2006-07-27

申请号：US11262294

申请日：2005-10-28

申请人： Michelangelo Pisasale ,  Maurizio Gaibotti ,  Michele La Placa

发明人： Michelangelo Pisasale ,  Maurizio Gaibotti ,  Michele La Placa

IPC分类号： G11C16/04

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A voltage-down converter for providing an output voltage lower than a power supply voltage of the converter is proposed. The converter includes voltage regulation means for obtaining an intermediate voltage corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element with a control signal resulting from a comparison between the intermediate voltage and a reference voltage, and an output stage for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set of multiple basic modules, the converter further including means for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.

摘要翻译： 提出了一种用于提供低于转换器的电源电压的输出电压的降压转换器。 转换器包括电压调节装置，用于通过由中间电压和参考电压之间的比较产生的控制信号控制可变电导率元件，从而获得与电源电压相对应的输出电压的中间电压，以及用于 通过利用所述控制信号控制另外的可变导电性元件从所述电源电压获得所述输出电压，其中所述另外的可变导电元件具有至少一组多个基本模块的模块化结构，所述转换器还包括用于使能 和/或根据输出电压和中间电压之间的比较来连续地禁用每组的模块。