公开(公告)号：US10942861B2

公开(公告)日：2021-03-09

申请号：US16049269

申请日：2018-07-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton

IPC: G06F12/10 ,  G06F3/06

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (IO) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

公开(公告)号：US10922098B2

公开(公告)日：2021-02-16

申请号：US15726305

申请日：2017-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  Jeremy Chritz ,  David Hulton

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/448 ,  G06F8/30 ,  G06F9/445

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

公开(公告)号：US11893398B2

公开(公告)日：2024-02-06

申请号：US17673712

申请日：2022-02-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  Tamara Schmitz ,  Fa-Long Luo ,  David Hulton

IPC: G06F9/38 ,  G06F9/448 ,  G06F12/0842 ,  G06F15/82 ,  G06F9/50

CPC classification number: G06F9/4494 ,  G06F9/3836 ,  G06F9/3891 ,  G06F9/5027 ,  G06F12/0842 ,  G06F15/825

Abstract: Methods, apparatuses, and systems for implementing data flows in a processor are described herein. A data flow manager may be configured to generate a configuration packet for a compute operation based on status information regarding multiple processing elements of the processor. Accordingly, multiple processing elements of a processor may concurrently process data flows based on the configuration packet. For example, the multiple processing elements may implement a mapping of processing elements to memory, while also implementing identified paths, through the processor, for the data flows. After executing the compute operation at certain processing elements of the processor, the processing results may be provided. In speech signal processing operations, the processing results may be compared to phonemes to identify such components of human speech in the processing results. Once dynamically identified, the processing elements may continue comparing additional components of human speech to facilitate processing of an audio recording, for example.

公开(公告)号：US20230205430A1

公开(公告)日：2023-06-29

申请号：US17694355

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Aaron Boehm ,  Jeremy Chritz ,  David Hulton ,  Tamara Schmitz ,  Max Vohra

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for verification of a volatile memory, such as a dynamic random-access memory (DRAM), using a unique identifier (ID) are described. A memory device may store a unique ID for a DRAM component of the memory device in non-volatile memory (e.g., in the DRAM, external to the DRAM). A host device coupled with the memory device may store, to non-volatile memory at the host device, information for verifying the identity of the DRAM component, for example, based on the unique ID. The memory device and host device may perform a procedure for verification of the identity of the DRAM component using the unique ID of the DRAM and the verification information stored at the host device. If the host device detects that the DRAM has been replaced or modified based on the verification procedure, the host device may disable one or more features of the memory device.

公开(公告)号：US11669344B2

公开(公告)日：2023-06-06

申请号：US16117529

申请日：2018-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  Jeremy Chritz ,  David Hulton

IPC: G06F15/80 ,  G06F9/448 ,  G06F9/30 ,  G06F8/30 ,  G06F9/445

CPC classification number: G06F9/4496 ,  G06F8/31 ,  G06F9/30007 ,  G06F9/30109 ,  G06F9/44505 ,  G06F15/80

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

公开(公告)号：US20230119361A1

公开(公告)日：2023-04-20

申请号：US18068419

申请日：2022-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton ,  Tamara Schmitz

IPC: H04L9/08 ,  H04L9/32 ,  H03K19/17768

Abstract: Examples described herein provide for attestation of memory dies using a respective memory identifier of the memory die itself. A memory device may include a memory die with a memory array, attestation logic, and programmable circuitry that stores a memory identifier associated with the memory array. The attestation logic may generate an encryption key pair based on the memory identifier stored in the programmable circuitry. Advantageously, by attesting memory die using a memory identifier stored in programmable circuitry, examples of systems and methods described herein may provide increased security for data processed by memory die. For example, a non-attested or compromised memory die may be remediated. The attestation of memory dies may include attestation of memory dies on wireless devices, drones, vehicles, and/or Internet-of-Things devices.

公开(公告)号：US11449276B2

公开(公告)日：2022-09-20

申请号：US17016023

申请日：2020-09-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton ,  Jeremy Chritz ,  Tamara Schmitz

IPC: G06K9/62 ,  G06F3/06 ,  G06F13/16 ,  H04L9/06 ,  G06N3/08

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

公开(公告)号：US11190441B2

公开(公告)日：2021-11-30

申请号：US16709033

申请日：2019-12-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  David Hulton ,  John Schroeter ,  John Watson

IPC: H04L12/721 ,  H04L12/715 ,  H04L12/733 ,  H04L12/707

Abstract: A device comprising a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip comprises a first and a second plurality of processing elements. The first plurality of processing elements operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.

公开(公告)号：US11176281B2

公开(公告)日：2021-11-16

申请号：US16154705

申请日：2018-10-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton ,  Jeremy Chritz

IPC: G06F21/00 ,  G06F21/76 ,  G06F15/78 ,  G06F21/60

Abstract: An apparatus, and a method therefore, are described, the apparatus according to one embodiment including a security manager and a plurality of clusters of processing elements. Each cluster of the plurality of clusters includes a respective plurality of processing elements. A controller of the apparatus, which may include a security manager, may be configured to control the plurality of clusters to receive a first data stream and a second data stream, control a first plurality of processing elements in a first cluster to process the first data stream using a first security protocol, and control a second plurality of processing elements in a second cluster to process the second data stream using a second security protocol.

公开(公告)号：US12124833B2

公开(公告)日：2024-10-22

申请号：US17744350

申请日：2022-05-13

Applicant: Micron Technology, Inc.

Inventor： Niccolo Izzo ,  Alessandro Orlando ,  Danilo Caraccio ,  David Hulton

IPC: G06F8/65 ,  H04L9/08

CPC classification number: G06F8/65 ,  H04L9/088

Abstract: Methods, systems, and devices for techniques for managing offline identity upgrades are described. A memory system may receive a command to update a device identifier for a device identifier composition engine (DICE) associated with the memory system. The memory system may generate an updated device identifier, at a first software layer of a set of software layers of the DICE, based on receiving the command. The memory system may decrypt a device specific key (DSK) stored at a read-only memory device of the memory system based on the received command, and sign the updated device identifier using the DSK based on decrypting the DSK. The memory system may execute one or more operations associated with the first software layer of the set of software layers of the DICE based on the signed updated device identifier.