公开(公告)号：US20220172778A1

公开(公告)日：2022-06-02

申请号：US17108763

申请日：2020-12-01

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

IPC: G11C13/00

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

公开(公告)号：US10608621B2

公开(公告)日：2020-03-31

申请号：US16050978

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Jeffrey E. Koelling

IPC: H03K5/15 ,  H03K5/156 ,  G11C7/22 ,  H03K5/159

Abstract: The present disclosure relates generally to improved systems and methods for control of one or more timing signals in a memory device. More specifically, the present disclosure relates to configurable duty cycle correction at one or more DQ pins (e.g., data input/output (I/O) pins) of the memory device. For example, the memory device may include a configurable phase splitter and/or selective capacitive loading circuitry implemented to adjust the duty cycle of a timing signal at one or more DQ pins during and/or after manufacture of the memory device. Accordingly, the memory device may include increased flexibility and granularity of control over the one or more timing signals.

公开(公告)号：US20200042423A1

公开(公告)日：2020-02-06

申请号：US16600355

申请日：2019-10-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Jason M. Brown ,  Derek R. May ,  Jeffrey E. Koelling ,  Roger D. Norwood

IPC: G06F11/34 ,  G11C11/408 ,  G11C11/406

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.