公开(公告)号：US20240354189A1

公开(公告)日：2024-10-24

申请号：US18608758

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

IPC: G06F11/10

CPC classification number: G06F11/1004

Abstract: In some implementations, the techniques described herein relate to a method including: receiving a codeword, the codeword having a first portion and a second portion, the first portion including user data and the second portion including synthesized data; detecting, using an ECC engine, at least one error in the codeword at a first position; and signaling an error misdetection when the first position is within the second portion.

公开(公告)号：US12068016B2

公开(公告)日：2024-08-20

申请号：US17712948

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G11C7/10 ,  G11C16/34

CPC classification number: G11C11/2275 ,  G11C7/1006 ,  G11C11/221 ,  G11C11/2273 ,  G11C16/34

Abstract: The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.

公开(公告)号：US20240184455A1

公开(公告)日：2024-06-06

申请号：US18513291

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： Andrea Vigilante ,  Riccardo Muzzetto

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for read training for non-volatile memory are described. In some examples, a memory system may perform read training by receiving a read command and reading a first subset of data. The memory system may apply one or more delays to each byte of the first subset of data and may select a delay for reading a second subset of data. Upon selecting the delay, the memory system may read the second subset of data using the selected delay.

公开(公告)号：US20240177792A1

公开(公告)日：2024-05-30

申请号：US18521891

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/42

CPC classification number: G11C29/46 ,  G11C29/1201 ,  G11C29/42

Abstract: Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases:



storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array;
reading from said counter the value corresponding to the number of bits having the predetermined logic value;
reading the data stored in the array of memory cells by applying a ramp of biasing voltages;
counting the number of bits having the predetermined logic value during the data reading phase;
stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.

公开(公告)号：US20240071483A1

公开(公告)日：2024-02-29

申请号：US17898392

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Francesco Mastroianni ,  Andrea Martinelli ,  Efrem Bolandrina ,  Lucia Di Martino ,  Riccardo Muzzetto ,  Zhongyuan Lu ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C11/56 ,  G06F3/06 ,  G06F12/02

CPC classification number: G11C11/5628 ,  G06F3/0679 ,  G06F12/0246

Abstract: Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.

公开(公告)号：US11901029B2

公开(公告)日：2024-02-13

申请号：US18112307

申请日：2023-02-21

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/14 ,  G11C29/20 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C7/14 ,  G11C29/12005 ,  G11C29/20 ,  G11C29/44

Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.

公开(公告)号：US20240038322A1

公开(公告)日：2024-02-01

申请号：US17873991

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Michele Maria Venturini ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Christophe Vincent Antoine Laurent ,  Christian Caillat

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5004

Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

公开(公告)号：US11776590B2

公开(公告)日：2023-10-03

申请号：US17748866

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

CPC classification number: G11C7/1009 ,  G11C7/06 ,  G11C7/1012 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.

公开(公告)号：US20230084481A1

公开(公告)日：2023-03-16

申请号：US18056516

申请日：2022-11-17

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G06F11/07

Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

公开(公告)号：US11495321B2

公开(公告)日：2022-11-08

申请号：US17387335

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/44 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02

Abstract: Methods, systems, and devices for method for setting a reference voltage for read operations are described. A memory device may perform a first read operation on a set of memory cells using a first reference voltage and detect a first codeword based on performing the first read operation using the first reference voltage. The memory device may compare a first quantity of bits of the first codeword having a first logic value (e.g., a logic value ‘1’) with an expected quantity of bits having the first logic value (e.g., the expected quantity of logic value ‘1’s stored by the set of memory cells). The memory device may determine whether to perform a second read operation on the set of memory cells using a second reference voltage different than the first reference voltage (e.g., greater or less than the first reference voltage) based on the comparing.