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    Effective avoidance of line cache misses
    13.
    发明授权
    Effective avoidance of line cache misses 有权

    公开(公告)号：US11734184B2

    公开(公告)日：2023-08-22

    申请号：US17687103

    申请日：2022-03-04

    Applicant: Micron Technology, Inc.

    Inventor： Meng Wei ,  Shi Bo Zhang ,  Tao Xiong

    IPC: G06F12/0891 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/14

    CPC classification number: G06F12/0891 ,  G06F12/0238 ,  G06F12/0848 ,  G06F12/1458 ,  G06F2212/1021

    Abstract: A system includes a line cache, a memory device, and a processing device operatively coupled to the line cache and the memory device, The processing device includes a buffer manager and a high-speed mode driver, the processing device to perform operations including: detecting that a received event is located in an events list, wherein events stored in the events list are associated with a set of functions that are known to cause a clock domain crossing between the buffer manager and a host system; enabling access to the line cache; and running, using the high-speed mode driver, in a high-speed mode to execute the set of functions out of the line cache on behalf of the host system.

    REDUNDANCY METADATA FOR MULTI-PLANE MEMORY ACCESS FAILURE
    15.
    发明申请
    REDUNDANCY METADATA FOR MULTI-PLANE MEMORY ACCESS FAILURE 有权

    公开(公告)号：US20230058217A1

    公开(公告)日：2023-02-23

    申请号：US17407898

    申请日：2021-08-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Meng Wei

    IPC: G06F3/06 ,  G06F11/14

    Abstract: A first data item is programmed to a first set of logical units of a memory sub-system. The first set of logical units is associated with a first fault tolerant stripe. A second data item is programmed to a second set of logical units of a memory sub-system. The second set of logical units is associated with a second fault tolerant stripe. A first set of redundancy metadata corresponding to the first data item and a second set of redundancy metadata corresponding to the second data item is generated. A combined set of redundancy metadata is generated based on at least the first set of redundancy metadata and the second set of redundancy metadata. The combined set of redundancy metadata is stored at a specified memory device of the memory sub-system.

    Optimizing garbage collection that uses a logical-to-physical table search
    16.
    发明授权
    Optimizing garbage collection that uses a logical-to-physical table search 有权

    公开(公告)号：US11556467B1

    公开(公告)日：2023-01-17

    申请号：US17396310

    申请日：2021-08-06

    Applicant: Micron Technology, inc.

    Inventor： Meng Wei

    IPC: G06F12/02 ,  G06F12/0882 ,  G06F3/06

    Abstract: A method is described that includes determining, by a memory subsystem, that a garbage collection process is to be performed on a memory device and selecting a first candidate block stripe for folding into a first target block stripe in response to determining that the garbage collection process is to be performed. The method further includes determining, by the memory subsystem, that a physical-to-logical table stored in the first candidate block stripe is unavailable; reducing a write command rate, which controls a rate at which writes are fulfilled by the memory subsystem, in response to determining that the physical-to-logical table stored in the first candidate block stripe is unavailable; and performing folding of the first candidate block stripe into the first target block stripe using a logical-to-physical table.

    Smart swapping and effective encoding of a double word in a memory sub-system
    17.
    发明授权
    Smart swapping and effective encoding of a double word in a memory sub-system 有权

    公开(公告)号：US12236118B2

    公开(公告)日：2025-02-25

    申请号：US18541683

    申请日：2023-12-15

    Applicant: Micron Technology, Inc.

    Inventor： Meng Wei

    IPC: G06F3/06

    Abstract: A processing device identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field; identifies a second set of bits associated with the translation unit, wherein the second set of bits corresponds to a block field; updates a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value; updates a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number; determines, based on the updated first portion and the updated second portion, that a swapping condition is satisfied; and performs a data access operation on a set of memory cells residing at a location corresponding to the translation unit.

    BALANCING WEAR ACROSS MULTIPLE RECLAIM GROUPS
    18.
    发明申请
    BALANCING WEAR ACROSS MULTIPLE RECLAIM GROUPS 有权

    公开(公告)号：US20250013368A1

    公开(公告)日：2025-01-09

    申请号：US18747582

    申请日：2024-06-19

    Applicant: Micron Technology, Inc.

    Inventor： Daniel J. Hubbard ,  Meng Wei

    IPC: G06F3/06

    Abstract: Aspects of the present disclosure configure a memory sub-system controller to balance program-erase count (PEC) across multiple reclaim groups of a memory sub-system. The controller groups a set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUs). The controller receives a request to program a set of data into a first RG of the plurality of RGs and compares a first PEC of the first RG with a second PEC of a second RG of the plurality of RGs. The controller performs wear leveling operations for the set of data requested to be programmed into the first RG using one or more memory components associated with the second RG based on a result of comparing the first PEC of the first RG with the second PEC of the second RG.

    FOLDING DATA USING VALID TRANSLATIONAL UNIT VALUES
    19.
    发明公开
    FOLDING DATA USING VALID TRANSLATIONAL UNIT VALUES 审中-公开

    公开(公告)号：US20240330177A1

    公开(公告)日：2024-10-03

    申请号：US18615069

    申请日：2024-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Meng Wei ,  Tom V. Geukens

    IPC: G06F12/02 ,  G06F13/16

    CPC classification number: G06F12/0292 ,  G06F12/0246 ,  G06F13/1626 ,  G06F2212/7201

    Abstract: Aspects of the present disclosure configure a memory sub-system controller to fold data based on valid translational unit count (VTC) values in a memory sub-system. The controller receives a request to perform a folding operation on data stored in an individual block stripe of the set of memory components. The controller retrieves, from a VTC table, a plurality of VTC values corresponding to a plurality of portions of the individual block stripe. The controller compares a first VTC value of the plurality of VTC values associated with a first of the plurality of portions to a second VTC value of the plurality of VTC values associated with a second of the plurality of portions. The controller performs the folding operation on a subset of the plurality of portions based on a result of comparing the first VTC value to the second VTC value.

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