公开(公告)号：US20230352098A1

公开(公告)日：2023-11-02

申请号：US18132489

申请日：2023-04-10

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Dheeraj Srinivasan ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Violante Moschiano

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/30

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, obtaining cell state information for each respective group of adjacent cells, for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells, and assigning each target cell of the set of target cells to the respective state information bin. Each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.

公开(公告)号：US20230012644A1

公开(公告)日：2023-01-19

申请号：US17946207

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/50

Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.

公开(公告)号：US11475969B2

公开(公告)日：2022-10-18

申请号：US17247633

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/50

Abstract: A system includes a memory array with sub-blocks, each sub-block having groups of memory cells. A processing device, operatively coupled with the memory array, is to perform operations including performing, after a wordline is programmed through the sub-blocks, scanning of the wordline. The scanning includes selecting, to sample first data of the wordline, a first group of the groups of memory cells of a first sub-block of the sub-blocks; selecting, to sample second data of the wordline, a second group of the groups of memory cells of a second sub-block of the sub-blocks; concurrently reading the first data from the first group and the second data from the second group of the groups of memory cells; and performing an error check of the wordline using the first data and the second data.

公开(公告)号：US20220199184A1

公开(公告)日：2022-06-23

申请号：US17247633

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/50 ,  G11C11/408 ,  G11C11/4074

Abstract: A system includes a memory array with sub-blocks, each sub-block having groups of memory cells. A processing device, operatively coupled with the memory array, is to perform operations including performing, after a wordline is programmed through the sub-blocks, scanning of the wordline. The scanning includes selecting, to sample first data of the wordline, a first group of the groups of memory cells of a first sub-block of the sub-blocks; selecting, to sample second data of the wordline, a second group of the groups of memory cells of a second sub-block of the sub-blocks; concurrently reading the first data from the first group and the second data from the second group of the groups of memory cells; and performing an error check of the wordline using the first data and the second data.