公开(公告)号：US20250124987A1

公开(公告)日：2025-04-17

申请号：US18990013

申请日：2024-12-20

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Thomas Fiala ,  Jian Huang ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/16

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations, including: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.

公开(公告)号：US20250156071A1

公开(公告)日：2025-05-15

申请号：US19022802

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Tomer Eliash ,  Sead Zildzic, JR.

IPC: G06F3/06

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

公开(公告)号：US20230352098A1

公开(公告)日：2023-11-02

申请号：US18132489

申请日：2023-04-10

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Dheeraj Srinivasan ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Violante Moschiano

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/30

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing a read operation to be initiated with respect to a set of target cells, obtaining cell state information for each respective group of adjacent cells, for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells, and assigning each target cell of the set of target cells to the respective state information bin. Each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.

公开(公告)号：US20240087655A1

公开(公告)日：2024-03-14

申请号：US17942977

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Thomas Fiala ,  Jian Huang ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/16

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/16

Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

公开(公告)号：US20240071484A1

公开(公告)日：2024-02-29

申请号：US18234429

申请日：2023-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Massimo Ernesto Bertuccio ,  Sead Zildzic, JR.

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10

Abstract: A memory device includes an array of memory cells, a plurality of access lines, and a controller. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line is connected to a control gate of a respective memory cell of each string of series-connected memory cells. The controller is configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a first target level. The controller is further configured to apply a first voltage level to a first access line connected to the selected memory cell, and apply a second voltage level higher than the first voltage level to a second access line adjacent to the first access line. The controller is further configured to apply a third voltage level between the first voltage level and the second voltage level to a third access line adjacent to the first access line and connected to an erased memory cell, and sense a first threshold voltage of the selected memory cell.

公开(公告)号：US20240020002A1

公开(公告)日：2024-01-18

申请号：US18221141

申请日：2023-07-12

Applicant: Micron Technology, Inc.

Inventor： Tomer Eliash ,  Sead Zildzic, JR.

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

公开(公告)号：US20230368845A1

公开(公告)日：2023-11-16

申请号：US18138489

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Z. Htet ,  Sead Zildzic, JR. ,  Thomas Fiala

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/102

Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

公开(公告)号：US20230307058A1

公开(公告)日：2023-09-28

申请号：US18110303

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Sead Zildzic, JR.

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/3459

Abstract: A first program pass of a multi-pass program operation is caused to be performed at a memory array. A first program voltage is applied to a wordline of a block of the memory array to program one or more memory cells during the first program pass. Subsequent to the first program pass of the multi-pass program operation, a pre-read operation is caused to be performed to read data corresponding to the first program pass and from the one or more memory cells. Whether a shift of a threshold voltage corresponding to the one or more memory cells satisfies a condition related to a threshold voltage change is determined based on the pre-read operation. Responsive to determining that the shift of the threshold voltage satisfies the condition, an updated second program voltage of a second program pass of the multi-pass program operation is determined.