公开(公告)号：US20250095713A1

公开(公告)日：2025-03-20

申请号：US18958966

申请日：2024-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US20230386556A1

公开(公告)日：2023-11-30

申请号：US17827582

申请日：2022-05-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ryo Fujimaki

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: Apparatuses and methods for arranging read data for output are described. An example apparatus includes a clock circuit, a data output circuit, and a control circuit. The clock circuit is configured to provide multiphase clock signals having different phases from each other based on a clock signal. The data output circuit is configured to receive a plurality of read data bits responsive to a read command and serially output each of the plurality of read data bits in synchronism with a corresponding one of the multiphase clock signals. The control circuit is configured to determine the correspondences between the plurality of read data bits and the multiphase clock signals based on information about which of the multiphase clock signals captures the read command.

公开(公告)号：US20230076261A1

公开(公告)日：2023-03-09

申请号：US17466052

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： Navya Sri Sreeram ,  Kallol Mazumder ,  Ryo Fujimaki ,  Kazutaka Miyano ,  Yutaka Uemura

IPC: G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076

Abstract: Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.

公开(公告)号：US20220100602A1

公开(公告)日：2022-03-31

申请号：US17037538

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Ryo Fujimaki

IPC: G06F11/10

Abstract: Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.