公开(公告)号：US11348633B2

公开(公告)日：2022-05-31

申请号：US17139310

申请日：2020-12-31

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano

IPC: G11C7/22 ,  G11C11/4076 ,  H03L7/081

Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.

公开(公告)号：US20210065782A1

公开(公告)日：2021-03-04

申请号：US16559344

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Yasuo Satoh ,  Kenji Mae

IPC: G11C11/406 ,  H03L7/081

Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.

公开(公告)号：US10924097B2

公开(公告)日：2021-02-16

申请号：US16834892

申请日：2020-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kazutaka Miyano

IPC: G11C8/00 ,  H03K5/135 ,  H03K5/133 ,  G11C8/10 ,  G11C8/18 ,  G11C7/22

Abstract: Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.

公开(公告)号：US20190386648A1

公开(公告)日：2019-12-19

申请号：US16012715

申请日：2018-06-19

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano

IPC: H03K5/135 ,  H03K5/133 ,  G11C7/22 ,  G11C8/10 ,  G11C8/18

Abstract: Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.

公开(公告)号：US20190244644A1

公开(公告)日：2019-08-08

申请号：US15890943

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Yoshiya Komatsu ,  Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/225 ,  G11C8/10 ,  H03L7/08

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.

公开(公告)号：US10290336B2

公开(公告)日：2019-05-14

申请号：US15595056

申请日：2017-05-15

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/02

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US09865317B2

公开(公告)日：2018-01-09

申请号：US15139102

申请日：2016-04-26

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C8/18 ,  G11C8/10

CPC classification number: G11C8/18 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/10 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/024 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US11594265B1

公开(公告)日：2023-02-28

申请号：US17466052

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： Navya Sri Sreeram ,  Kallol Mazumder ,  Ryo Fujimaki ,  Kazutaka Miyano ,  Yutaka Uemura

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C8/18

Abstract: Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.

公开(公告)号：US20170309320A1

公开(公告)日：2017-10-26

申请号：US15139102

申请日：2016-04-26

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/10 ,  G11C7/22

CPC classification number: G11C8/18 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/10 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/024 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US09531363B2

公开(公告)日：2016-12-27

申请号：US14698550

申请日：2015-04-28

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano

IPC: H03L7/06 ,  H03K5/135 ,  H03K5/14 ,  H03K3/037 ,  H03L7/081

CPC classification number: H03K5/135 ,  G11C7/106 ,  G11C7/1066 ,  G11C2207/2272 ,  H03K3/037 ,  H03K5/14 ,  H03L7/0812

Abstract: Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. The latch control circuit is configured to provide first control signals based on a count associated with the first clock signal. The latch control circuit is further configured to provide second control signals based on the count associated with the first clock signal. The second clock signals are delayed relative to the first clock signals by an amount substantially equal to a delay between the clock signal and the delayed clock signal. The example apparatus further includes a latch circuit configured to latch an input signal responsive to the first control signals. The latch circuit is further configured to provide the latched signal to an output responsive to the second control signals.

Abstract translation: 描述包括等待时间控制电路的方法和装置。 一种示例性装置包括：延迟线电路，被配置为延迟时钟信号;锁存器控制电路，被配置为接收时钟信号和延迟的时钟信号。 锁存器控制电路被配置为基于与第一时钟信号相关联的计数来提供第一控制信号。 锁存控制电路还被配置为基于与第一时钟信号相关联的计数来提供第二控制信号。 第二时钟信号相对于第一时钟信号被延迟大致等于时钟信号和延迟的时钟信号之间的延迟的量。 该示例设备还包括锁存电路，其被配置为响应于第一控制信号锁存输入信号。 锁存电路还被配置为响应于第二控制信号向锁存的信号提供锁存信号。