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公开(公告)号：US10403335B1
公开(公告)日：2019-09-03
申请号：US15997356
申请日：2018-06-04
发明人： Yutaka Uemura , Yasuhiro Takai
摘要： An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.
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公开(公告)号：US20230014446A1
公开(公告)日：2023-01-19
申请号：US17935016
申请日：2022-09-23
发明人： Yutaka Uemura
摘要： Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.
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公开(公告)号：US10424363B2
公开(公告)日：2019-09-24
申请号：US16026559
申请日：2018-07-03
发明人： Yutaka Uemura
IPC分类号： G11C11/406 , G11C5/06 , G11C5/14 , G11C11/408 , G11C11/4093 , G11C11/4091
摘要： Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically slacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.
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公开(公告)号：US20180315469A1
公开(公告)日：2018-11-01
申请号：US16026559
申请日：2018-07-03
发明人： Yutaka Uemura
IPC分类号： G11C11/406 , G11C11/4091 , G11C11/408
CPC分类号： G11C11/40615 , G11C5/06 , G11C5/14 , G11C11/40618 , G11C11/4087 , G11C11/4091 , G11C11/4093
摘要： Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically slacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.
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公开(公告)号：US11967358B2
公开(公告)日：2024-04-23
申请号：US17825600
申请日：2022-05-26
发明人： Yoshiya Komatsu , Yutaka Uemura
IPC分类号： G11C11/4076 , G11C11/4074 , G11C11/4093
CPC分类号： G11C11/4076 , G11C11/4074 , G11C11/4093
摘要： Apparatuses, systems, and methods for bias temperature instability (BTI) mitigation. A BTI oscillator provides a periodic BTI signal. A BTI logic circuit generates a BTI pulse signal based on the periodic BTI signal and synchronized to a clock signal. A clock gating circuit passes the clock signal to a clock path when the periodic BTI signal is active. When the memory is in an unclocked mode, where an external clock is not received, the periodic BTI signal is provided to a clock input buffer and passed as the clock signal.
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公开(公告)号：US11309047B2
公开(公告)日：2022-04-19
申请号：US17020529
申请日：2020-09-14
发明人： Yutaka Uemura
摘要： Disclosed herein is an apparatus that includes first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in synchronization with a clock signal, and a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit and set a frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.
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公开(公告)号：US20200013452A1
公开(公告)日：2020-01-09
申请号：US16571043
申请日：2019-09-13
发明人： Yutaka Uemura
IPC分类号： G11C11/406 , G11C5/06 , G11C5/14 , G11C11/4091 , G11C11/4093 , G11C11/408
摘要： Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically stacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.
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公开(公告)号：US10020046B1
公开(公告)日：2018-07-10
申请号：US15449688
申请日：2017-03-03
发明人： Yutaka Uemura
IPC分类号： G11C11/40 , G11C11/406 , G11C11/4091 , G11C11/408
摘要： Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second bank, the first bank and the second bank including memory cells; and a second die vertically stacked with the first die, the second die including a third bank and a fourth bank, the third bank and the fourth bank including memory cells. The third bank is vertically aligned with the first bank. The first bank and the fourth bank are configured to be refreshed prior to refreshing the second bank and the fourth bank.
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公开(公告)号：US11749324B2
公开(公告)日：2023-09-05
申请号：US17935016
申请日：2022-09-23
发明人： Yutaka Uemura
CPC分类号： G11C7/222 , G11C7/106 , G11C7/1036 , G11C7/1045 , G11C7/1087 , G11C29/10 , H03K23/002 , H03K23/52
摘要： Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.
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公开(公告)号：US11594265B1
公开(公告)日：2023-02-28
申请号：US17466052
申请日：2021-09-03
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C8/18
摘要： Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.
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