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公开(公告)号：US11594265B1
公开(公告)日：2023-02-28
申请号：US17466052
申请日：2021-09-03
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C8/18
摘要： Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.
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公开(公告)号：US20240062803A1
公开(公告)日：2024-02-22
申请号：US17890974
申请日：2022-08-18
发明人： William C. Waldrop , Liang Chen , Shingo Mitsubori , Ryo Fujimaki , Atsuko Momma
IPC分类号： G11C11/4076 , G11C11/4096
CPC分类号： G11C11/4076 , G11C11/4096
摘要： Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.
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公开(公告)号：US11526453B1
公开(公告)日：2022-12-13
申请号：US17401729
申请日：2021-08-13
发明人： Kallol Mazumder , Navya Sri Sreeram , Ryo Fujimaki
IPC分类号： G06F13/00 , G06F13/16 , G11C11/4076 , G06F1/10 , G06F11/10 , G11C11/4093
摘要： Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a read state circuit configured to control the schedule/timing associated with parallel pipelines, and (2) a timing control circuit configured to coordinate output of data from the parallel pipelines.
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公开(公告)号：US20230060064A1
公开(公告)日：2023-02-23
申请号：US17979679
申请日：2022-11-02
发明人： Kallol Mazumder , Navya Sri Sreeram , Ryo Fujimaki
IPC分类号： G06F13/16 , G11C11/4093 , G06F1/10 , G11C11/4076 , G06F11/10
摘要： Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a read state circuit configured to control the schedule/timing associated with parallel pipelines, and (2) a timing control circuit configured to coordinate output of data from the parallel pipelines.
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公开(公告)号：US11537462B2
公开(公告)日：2022-12-27
申请号：US17037538
申请日：2020-09-29
发明人： Ryo Fujimaki
摘要： Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.
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6.发明授权公开(公告)号：US11067628B2
公开(公告)日：2021-07-20
申请号：US16577267
申请日：2019-09-20
发明人： Chiaki Dono , Chikara Kondo , Ryo Fujimaki
IPC分类号： G01R31/00 , G01R31/3177 , G11C29/12 , H01L25/18 , G11C11/4093
摘要： Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.
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7.发明申请公开(公告)号：US20210088583A1
公开(公告)日：2021-03-25
申请号：US16577267
申请日：2019-09-20
发明人： Chiaki Dono , Chikara Kondo , Ryo Fujimaki
IPC分类号： G01R31/3177 , G11C11/4093 , H01L25/18 , G11C29/12
摘要： Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.
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公开(公告)号：US20230386556A1
公开(公告)日：2023-11-30
申请号：US17827582
申请日：2022-05-27
发明人： Ryo Fujimaki
IPC分类号： G11C11/4076 , G11C11/4093 , G11C11/4096
CPC分类号： G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： Apparatuses and methods for arranging read data for output are described. An example apparatus includes a clock circuit, a data output circuit, and a control circuit. The clock circuit is configured to provide multiphase clock signals having different phases from each other based on a clock signal. The data output circuit is configured to receive a plurality of read data bits responsive to a read command and serially output each of the plurality of read data bits in synchronism with a corresponding one of the multiphase clock signals. The control circuit is configured to determine the correspondences between the plurality of read data bits and the multiphase clock signals based on information about which of the multiphase clock signals captures the read command.
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公开(公告)号：US20230076261A1
公开(公告)日：2023-03-09
申请号：US17466052
申请日：2021-09-03
IPC分类号： G11C7/10 , G11C11/4096 , G11C7/22 , G11C11/4076
摘要： Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.
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公开(公告)号：US20220100602A1
公开(公告)日：2022-03-31
申请号：US17037538
申请日：2020-09-29
发明人： Ryo Fujimaki
IPC分类号： G06F11/10
摘要： Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.
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