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    Apparatuses and methods for cyclic redundancy calculation for semiconductor device
    3.
    发明授权
    Apparatuses and methods for cyclic redundancy calculation for semiconductor device 有权

    公开(公告)号：US11537462B2

    公开(公告)日：2022-12-27

    申请号：US17037538

    申请日：2020-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Ryo Fujimaki

    IPC: G06F11/10 ,  G06F11/22

    Abstract: Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.

    Replication of a first interface onto a second interface and related systems, methods, and devices
    4.
    发明授权
    Replication of a first interface onto a second interface and related systems, methods, and devices 有权

    公开(公告)号：US11067628B2

    公开(公告)日：2021-07-20

    申请号：US16577267

    申请日：2019-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Chiaki Dono ,  Chikara Kondo ,  Ryo Fujimaki

    IPC: G01R31/00 ,  G01R31/3177 ,  G11C29/12 ,  H01L25/18 ,  G11C11/4093

    Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

    REPLICATION OF A FIRST INTERFACE ONTO A SECOND INTERFACE AND RELATED SYSTEMS, METHODS, AND DEVICES
    5.
    发明申请
    REPLICATION OF A FIRST INTERFACE ONTO A SECOND INTERFACE AND RELATED SYSTEMS, METHODS, AND DEVICES 有权

    公开(公告)号：US20210088583A1

    公开(公告)日：2021-03-25

    申请号：US16577267

    申请日：2019-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Chiaki Dono ,  Chikara Kondo ,  Ryo Fujimaki

    IPC: G01R31/3177 ,  G11C11/4093 ,  H01L25/18 ,  G11C29/12

    Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

    SEMICONDUCTOR DEVICE PERFORMING LOOPBACK OPERATION
    6.
    发明申请
    SEMICONDUCTOR DEVICE PERFORMING LOOPBACK OPERATION 有权

    公开(公告)号：US20250157526A1

    公开(公告)日：2025-05-15

    申请号：US18780106

    申请日：2024-07-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yuichiro Sato ,  Shingo Mitsubori ,  Ryo Fujimaki

    IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

    Abstract: An example apparatus includes a first circuit configured to receive a plurality of first write data and then a plurality of second write data responsive to a write command; a second circuit configured to select one or ones of the plurality of first write data and one or ones of the plurality of second write data based, at least in part, on a first selection signal and a second selection signal following the first selection signal, respectively; and a third circuit configured to: receive an internal write command signal provided correspondingly to the write command; mask a portion of the internal write command signal a timing of which partially overlaps the plurality of first write data to provide a masked internal write command signal; and provide the second selection signal based, at least in part, on the second internal command signal.

    Apparatuses and methods for a per-DRAM addressability synchronizer circuit
    7.
    发明授权
    Apparatuses and methods for a per-DRAM addressability synchronizer circuit 有权

    公开(公告)号：US12183385B2

    公开(公告)日：2024-12-31

    申请号：US17890974

    申请日：2022-08-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

    IPC: G11C11/4096 ,  G11C11/4076

    Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

    APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER CIRCUIT
    8.
    发明公开
    APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER CIRCUIT 审中-公开

    公开(公告)号：US20240062803A1

    公开(公告)日：2024-02-22

    申请号：US17890974

    申请日：2022-08-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

    IPC: G11C11/4076 ,  G11C11/4096

    CPC classification number: G11C11/4076 ,  G11C11/4096

    Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

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