公开(公告)号：US11823729B2

公开(公告)日：2023-11-21

申请号：US17491422

申请日：2021-09-30

Applicant: Micron Technology, Inc.

Inventor： Liang Chen

IPC: G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  G06F13/28 ,  G11C29/56 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F13/28 ,  G11C29/023 ,  G11C29/56012 ,  G11C7/1039 ,  G11C7/222

Abstract: Systems and methods for gating, via clock gating circuitry, a clock signal based at least in part on a mode register value indicative of synchronization of a command address signal with the clock signal when the mode register value indicates synchronization of the command address signal with the clock signal has not occurred. The clock gating circuitry is configured to, gate the clock signal based at least in part on the mode register value and a chip select signal value when the mode register value indicates synchronization of the command address signal with the clock signal has occurred.

公开(公告)号：US10770116B2

公开(公告)日：2020-09-08

申请号：US16446876

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Liang Chen

IPC: G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L25/065 ,  G11C7/10

Abstract: A memory device includes active circuitry configured to process a segment set that corresponds to a source data, wherein: the source data comprises information corresponding to a device operation, the source data having a block length representing a number of bits therein, and the segment set includes at least a first segment and a second segment, the first segment and the second segment each including number of bits less than the block length; and a set of die pads coupled to the active circuitry and configured to communicate the segment set for operating a second device, wherein the set includes a number of die pads less than the block length.

公开(公告)号：US10607671B2

公开(公告)日：2020-03-31

申请号：US15955330

申请日：2018-04-17

Applicant: Micron Technology, Inc.

Inventor： Liang Chen ,  Ming-Bo Liu

IPC: G11C7/04 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10 ,  G11C11/4096 ,  H04L25/03 ,  G06F13/18 ,  G11C11/4074

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.

公开(公告)号：US20190391763A1

公开(公告)日：2019-12-26

申请号：US16534846

申请日：2019-08-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408

Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.

公开(公告)号：US20190259431A1

公开(公告)日：2019-08-22

申请号：US16051189

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/10 ,  H04L25/03 ,  G11C7/22

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

公开(公告)号：US20190244645A1

公开(公告)日：2019-08-08

申请号：US15891353

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G11C8/18 ,  G11C7/10 ,  G06F13/16 ,  G06F13/42 ,  G11C29/50 ,  G06F5/06

Abstract: Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.

公开(公告)号：US20250095713A1

公开(公告)日：2025-03-20

申请号：US18958966

申请日：2024-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US10672441B2

公开(公告)日：2020-06-02

申请号：US16051202

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10 ,  G11C11/4096 ,  H04L25/03 ,  G06F13/18 ,  G11C11/4074

Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.

公开(公告)号：US10664173B2

公开(公告)日：2020-05-26

申请号：US15883956

申请日：2018-01-30

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Liang Chen ,  Daniel B. Penney

IPC: G11B5/00 ,  G06F3/06

Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.

公开(公告)号：US20200082856A1

公开(公告)日：2020-03-12

申请号：US16683018

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4074 ,  G06F13/18 ,  H04L25/03 ,  G11C11/4096 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4093 ,  G11C11/4076

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.