公开(公告)号：US12008265B2

公开(公告)日：2024-06-11

申请号：US17648400

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Saira Samar Malik ,  Sahil Soi ,  Taeksang Song

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for quality-of-service information for a multi-memory system are described. An interface controller may receive a first command from a host device during a set of clock cycles. The first command may be received over a command bus that includes a pin, such as a command select pin configured for double data rate signaling. The interface controller may decode the first command based on a state of the command select pin during at least one clock cycle of the set of clock cycles. And the interface controller may determine quality-of-service information for a second command based on decoding the first command and on information, such as a plurality of bits, included in the first command.

公开(公告)号：US11899944B2

公开(公告)日：2024-02-13

申请号：US17648398

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Saira Samar Malik ,  Chinnakrishnan Ballapuram ,  Taeksang Song

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for strategic power mode transition in a multi-memory device are described. A controller may receive, from a host device, a command indicating that the controller is to transition a volatile memory and a non-volatile memory from respective deep sleep modes. In a first example, the controller may respond to the command by transitioning the volatile memory to a standby power mode for the volatile memory and transitioning the non-volatile memory to an intermediate power mode for the non-volatile memory that consumes less power than a standby mode for the non-volatile memory. In a second example, the controller may respond to the command by transitioning the volatile memory to the standby power mode for the volatile memory and maintain the non-volatile memory in the deep sleep mode until a condition, such as a miss, occurs.

公开(公告)号：US20230055293A1

公开(公告)日：2023-02-23

申请号：US17648404

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira Samar Malik ,  Chinnakrishnan Ballapuram

IPC: G06F11/10 ,  G06F9/30

Abstract: Methods, systems, and devices for post error correction code (ECC) registers for cache metadata are described. A device may read metadata from a memory array included in the device. The metadata may include information for operating a volatile memory as a cache for a non-volatile memory. The device may perform an ECC operation on the metadata based on reading the metadata from the memory array. After performing the ECC operation on the metadata, the device may write the metadata to a register that is coupled with the memory array. The device may then write the metadata from the register to the memory array.

公开(公告)号：US20220035567A1

公开(公告)日：2022-02-03

申请号：US17385453

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Chinnakrishnan Ballapuram ,  Saira Samar Malik

IPC: G06F3/06

Abstract: Methods, systems, and devices for transaction management based on metadata are described. A host device may transmit a read command to a memory device. Based on the read command, the host device may receive a set of data from the memory device. The host device may also receive metadata associated with the set of data. Based on the metadata, the host device may determine whether the set of data is the data requested by the read command, data requested by a previous read command, or data unrequested by the host device, or some combination. If the set of data is the data requested by the read command or a previous read command, the host device may process the set of data accordingly. If the set of data is data unrequested by the host device, the host device may discard the set of data and retransmit the read command.

公开(公告)号：US20210398601A1

公开(公告)日：2021-12-23

申请号：US17349612

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Hyunyoo Lee ,  Saira Samar Malik ,  Kang-Yong Kim

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/12 ,  G11C29/14 ,  G11C29/18

Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

公开(公告)号：US12056395B2

公开(公告)日：2024-08-06

申请号：US17456994

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Chinnakrishnan Ballapuram ,  Saira Samar Malik

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0868

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0238 ,  G06F12/0868

Abstract: Methods, systems, and devices for improved techniques for partial writes are described. A memory device may include a non-volatile memory and a volatile memory configured to operate as a cache for the non-volatile memory. The memory device may receive, from a host device, a write command for a first data set provided by the host device. Based on the write command, the memory device may store the first data set in a buffer coupled with a volatile memory. After storing the first data set in the buffer, the memory device may communicate to the volatile memory a set of data that includes the first data set and a second data set. The first data set and the second data may be associated with adjacent addresses for the volatile memory and may each have sizes smaller than a threshold size associated with the volatile memory.

公开(公告)号：US11747992B2

公开(公告)日：2023-09-05

申请号：US17349634

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Taeksang Song ,  Kang-Yong Kim

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7211

Abstract: Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.

公开(公告)号：US11587633B2

公开(公告)日：2023-02-21

申请号：US17349612

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Hyunyoo Lee ,  Saira Samar Malik ,  Kang-Yong Kim

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/14 ,  G11C29/18 ,  G11C29/12

Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

公开(公告)号：US11526442B2

公开(公告)日：2022-12-13

申请号：US17390097

申请日：2021-07-30

Applicant: Micron Technology, Inc.

Inventor： Chinnakrishnan Ballapuram ,  Taeksang Song ,  Saira Samar Malik

IPC: G06F12/00 ,  G06F12/0802 ,  G06F3/06

Abstract: Methods, systems, and devices for metadata management for a cache are described. An interface controller may include a first array and a second array that store metadata for a cache memory. The interface controller may receive an activate command associated with a row of the cache memory. In response to the activate command, the interface controller may communicate storage information for the row of the volatile memory from a first array to a first register. The interface controller may receive an access command associated with the row of the cache memory. In response to the access command and based on the storage information in the first register, the interface controller may communicate validity information for the row from a second array to the first register or dirty information for the row from the second array to a second register.

公开(公告)号：US20220350535A1

公开(公告)日：2022-11-03

申请号：US17585298

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira Samar Malik ,  Chinnakrishnan Ballapuram

IPC: G06F3/06

Abstract: Methods, systems, and devices for power mode control in a multi-memory device are described. An apparatus may include a non-volatile memory and a volatile memory. The apparatus may operate the volatile memory in a first power mode and the non-volatile memory in a second power mode. The apparatus may transition the volatile memory from the first power mode to a third power mode based on a power mode command from a host device. The apparatus may transition the non-volatile memory from the second power mode to a fourth power mode that consumes less power than the second power mode irrespective of the command from the host device and based on a quantity of queued commands for the non-volatile memory being less than a threshold quantity.