公开(公告)号：US20230236931A1

公开(公告)日：2023-07-27

申请号：US17894886

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Lingming Yang ,  Amitava Majumdar ,  Sandeep Krishna Thirumala ,  Nevil Gajera

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0689

Abstract: Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.

公开(公告)号：US20230195624A1

公开(公告)日：2023-06-22

申请号：US17556891

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Sandeep Krishna Thirumala ,  Lingming Yang ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60 ,  G06F2212/72

Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.