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公开(公告)号：US20230236934A1
公开(公告)日：2023-07-27
申请号：US17894893
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Amitava Majumdar , Sandeep Krishna Thirumala , Nevil Gajera
CPC classification number: G06F11/1096 , G06F3/0619 , G06F3/0659 , G06F3/0689
Abstract: Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.
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公开(公告)号：US11775431B2
公开(公告)日：2023-10-03
申请号：US17556891
申请日：2021-12-20
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Sandeep Krishna Thirumala , Lingming Yang , Karthik Sarpatwari , Nevil N. Gajera
IPC: G06F12/08 , G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/60 , G06F2212/72
Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.
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公开(公告)号：US12032482B2
公开(公告)日：2024-07-09
申请号：US17843282
申请日：2022-06-17
Applicant: Micron Technology, Inc.
Inventor： Sandeep Krishna Thirumala
IPC: G06F12/00 , G06F12/0864 , G06F21/55
CPC classification number: G06F12/0864 , G06F21/554 , G06F2212/6032
Abstract: Systems, apparatuses, and methods related to a memory controller for performing row access tracking to mitigate row hammer attacks. A memory controller comprises a dual cache system including a direct mapped cache and a victim cache. The direct mapped cache functions as the main cache while a fully associative victim cache is used to reduce hammer attacks to targeted rows. The direct mapped cache performs an aliasing operation to map at least a portion of data stored in a memory device to the direct mapped cache. The direct mapped cache also uses a plurality of counters operatively coupled to the direct mapped cache to track and monitor the number of activations of the data stored in the direct mapped cache. The memory controller proactively refreshes all adjacent rows in the memory device when the respective counter of the direct mapped cache exceeds a predetermined threshold.
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公开(公告)号：US12019516B2
公开(公告)日：2024-06-25
申请号：US17894886
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Amitava Majumdar , Sandeep Krishna Thirumala , Nevil Gajera
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0659 , G06F3/0689 , G06F11/1096
Abstract: Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.
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公开(公告)号：US20230238049A1
公开(公告)日：2023-07-27
申请号：US17844450
申请日：2022-06-20
Applicant: Micron Technology, Inc.
Inventor： Sandeep Krishna Thirumala , Amitava Majumdar , Lingming Yang , Nevil Gajera
IPC: G11C11/408 , G11C11/4094 , G11C11/4096 , G06F12/02 , G06F11/10
CPC classification number: G11C11/4085 , G11C11/4094 , G11C11/4096 , G06F12/0238 , G06F11/1068 , G06F2212/7201
Abstract: Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.
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Patent Agency Ranking
公开(公告)号：US20230195623A1
公开(公告)日：2023-06-22
申请号：US17556862
申请日：2021-12-20
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Sandeep Krishna Thirumala , Lingming Yang , Karthik Sarpatwari , Nevil N. Gajera
IPC: G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/72 , G06F2212/60
Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.
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7.发明授权公开(公告)号：US12032443B2
公开(公告)日：2024-07-09
申请号：US18156340
申请日：2023-01-18
Applicant: Micron Technology, Inc.
Inventor： Sandeep Krishna Thirumala , Lingming Yang , Amitava Majumdar , Nevil Gajera
CPC classification number: G06F11/1076 , G06F11/1004 , G06F13/4221
Abstract: Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.
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8.发明授权公开(公告)号：US12013756B2
公开(公告)日：2024-06-18
申请号：US17894893
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Lingming Yang , Amitava Majumdar , Sandeep Krishna Thirumala , Nevil Gajera
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0659 , G06F3/0689 , G06F11/1096
Abstract: Provided is a memory system including a plurality of memory submodules and a controller. Each submodule comprises a plurality of memory channels, each channel having a parity bit and a redundant array of independent devices (RAID) parity channel. The controller is configured to receive a block of data for storage in the plurality of memory submodules and determine whether a level of data traffic demand for a first of the plurality of submodules is high or low. When the data traffic demand is low, (i) writing a portion of the block of data in the first of the plurality of submodules and (ii) concurrently updating the parity bit and the RAID parity channel associated with the block of data. When the data traffic demand is high, (i) only writing the portion of the block of data in the first of the plurality of submodules and (ii) deferring updating of the parity bits and the RAID parity channel associated with the block of data.
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公开(公告)号：US11782830B2
公开(公告)日：2023-10-10
申请号：US17556862
申请日：2021-12-20
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Sandeep Krishna Thirumala , Lingming Yang , Karthik Sarpatwari , Nevil N. Gajera
IPC: G06F12/00 , G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/60 , G06F2212/72
Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.
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公开(公告)号：US20230236982A1
公开(公告)日：2023-07-27
申请号：US17843282
申请日：2022-06-17
Applicant: Micron Technology, Inc.
Inventor： Sandeep Krishna Thirumala
IPC: G06F12/0864 , G06F21/55
CPC classification number: G06F12/0864 , G06F21/554 , G06F2212/6032
Abstract: Systems, apparatuses, and methods related to a memory controller for performing row access tracking to mitigate row hammer attacks. A memory controller comprises a dual cache system including a direct mapped cache and a victim cache. The direct mapped cache functions as the main cache while a fully associative victim cache is used to reduce hammer attacks to targeted rows. The direct mapped cache performs an aliasing operation to map at least a portion of data stored in a memory device to the direct mapped cache. The direct mapped cache also uses a plurality of counters operatively coupled to the direct mapped cache to track and monitor the number of activations of the data stored in the direct mapped cache. The memory controller proactively refreshes all adjacent rows in the memory device when the respective counter of the direct mapped cache exceeds a predetermined threshold.
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