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公开(公告)号：US20240201252A1
公开(公告)日：2024-06-20
申请号：US18535640
申请日：2023-12-11
Applicant: Micron Technology, Inc.
Inventor： John M. Gonzales , Seth A. Eichmeyer , Atsuko Otsuka , Takeshi Kaku , Soeparto Tandjoeng
IPC: G01R31/311
CPC classification number: G01R31/311
Abstract: An example method can include focusing a light source onto a circuit of a first memory die of a plurality of memory dies. A light of the light source can reach the circuit of the memory die and can be reflected back toward a sensor. The method can further include receiving the reflection of light from the circuit at the sensor. The method can further include determining whether the circuit is transferring a particular signal based on the reflected light.
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公开(公告)号：US11829243B2
公开(公告)日：2023-11-28
申请号：US17572129
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Jenkinson , Seth A. Eichmeyer , Christopher G. Wieduwilt
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/0793 , G06F11/3037
Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.
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公开(公告)号：US11694762B2
公开(公告)日：2023-07-04
申请号：US17466160
申请日：2021-09-03
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , James S. Rehmeyer , Seth A. Eichmeyer
CPC classification number: G11C29/44 , G11C11/409 , G11C29/027 , G11C29/18 , G11C29/789 , H03M13/1105 , H03M13/13
Abstract: Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.
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公开(公告)号：US20220139492A1
公开(公告)日：2022-05-05
申请号：US17647508
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , James S. Rehmeyer , Seth A. Eichmeyer
IPC: G11C29/00 , G11C11/408
Abstract: Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.
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公开(公告)号：US20210110881A1
公开(公告)日：2021-04-15
申请号：US16599796
申请日：2019-10-11
Applicant: Micron Technology, Inc.
Inventor： Seth A. Eichmeyer , Patrick Mullarkey
Abstract: Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.
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Patent Agency Ranking
公开(公告)号：US20250060893A1
公开(公告)日：2025-02-20
申请号：US18781102
申请日：2024-07-23
Applicant: Micron Technology, Inc.
IPC: G06F3/06
Abstract: Apparatuses, systems, and methods for tracking latch upset events using block status data are described. An example method includes tracking a block status of each of a plurality of blocks of a first memory device by storing a first set of block status data that indicates a status of each block of the plurality of blocks in the first memory device and storing a second set of block status data that indicates a status of each block of the plurality of blocks in a location. The example method further includes comparing the first set of block status data to the second set of block status data.
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公开(公告)号：US12223099B2
公开(公告)日：2025-02-11
申请号：US17706410
申请日：2022-03-28
Applicant: Micron Technology, Inc.
Inventor： Seth A. Eichmeyer , Christopher G. Wieduwilt , Matthew D. Jenkinson
Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.
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公开(公告)号：US20230315918A1
公开(公告)日：2023-10-05
申请号：US17706410
申请日：2022-03-28
Applicant: Micron Technology, Inc.
Inventor： Seth A. Eichmeyer , Christopher G. Wieduwilt , Matthew D. Jenkinson
Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.
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公开(公告)号：US11244741B1
公开(公告)日：2022-02-08
申请号：US17089002
申请日：2020-11-04
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , James S. Rehmeyer , Seth A. Eichmeyer
IPC: G11C29/00 , G11C11/40 , G11C11/408
Abstract: Memory devices are disclosed. A memory device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, and electronic systems are also disclosed.
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公开(公告)号：US11139045B2
公开(公告)日：2021-10-05
申请号：US16693126
申请日：2019-11-22
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , James S. Rehmeyer , Seth A. Eichmeyer
Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.
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