公开(公告)号：US20240201252A1

公开(公告)日：2024-06-20

申请号：US18535640

申请日：2023-12-11

Applicant: Micron Technology, Inc.

Inventor： John M. Gonzales ,  Seth A. Eichmeyer ,  Atsuko Otsuka ,  Takeshi Kaku ,  Soeparto Tandjoeng

IPC: G01R31/311

CPC classification number: G01R31/311

Abstract: An example method can include focusing a light source onto a circuit of a first memory die of a plurality of memory dies. A light of the light source can reach the circuit of the memory die and can be reflected back toward a sensor. The method can further include receiving the reflection of light from the circuit at the sensor. The method can further include determining whether the circuit is transferring a particular signal based on the reflected light.

公开(公告)号：US11854639B2

公开(公告)日：2023-12-26

申请号：US17719327

申请日：2022-04-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Atsuko Otsuka ,  Takeshi Kaku ,  Soeparto Tandjoeng

IPC: G11C29/18 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/18 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/1802

Abstract: Apparatuses and methods including a test circuit in a scribe region between chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chip, adjacent to one another; a scribe region between the first and second semiconductor chips; test address pads in the scribe region; and an address decoder circuit in the scribe region. The test address pads receive address signals. The address decoder provides first signals responsive to the address signals from the test address pads.

公开(公告)号：US20250123305A1

公开(公告)日：2025-04-17

申请号：US18784516

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Soeparto Tandjoeng ,  Takeshi Kaku ,  Atsuko Otsuka

IPC: G01R1/067 ,  G01R31/28 ,  H01L23/48 ,  H10B80/00

Abstract: An example apparatus can include a plurality of metal lines. The example apparatus can further include a cantilever, a diode, or a transistor in contact with at least a first metal line and a second metal line of the plurality of metal lines. The example apparatus can further include a circuit comprising at least one transistor or at least one diode in contact with at least the first metal line of the plurality of metal lines. The example apparatus can further include a diode or transistor in contact with at least the second metal line of the plurality of metal lines. An end of the cantilever is in contact with the first metal line through a first via and a first oxide portion. A portion of the cantilever is in contact with the second metal line through a second via and a second oxide portion.

公开(公告)号：US10833087B2

公开(公告)日：2020-11-10

申请号：US16107324

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn ,  Haitao Liu ,  Soichi Sugiura ,  Oscar O. Enomoto ,  Mark A. Zaleski ,  Keisuke Hirofuji ,  Makoto Morino ,  Ichiro Abe ,  Yoshiyuki Nanjo ,  Atsuko Otsuka

IPC: H01L27/00 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.

公开(公告)号：US20200066726A1

公开(公告)日：2020-02-27

申请号：US16107324

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn ,  Haitao Liu ,  Soichi Sugiura ,  Oscar O. Enomoto ,  Mark A. Zaleski ,  Keisuke Hirofuji ,  Makoto Morino ,  Ichiro Abe ,  Yoshiyuki Nanjo ,  Atsuko Otsuka

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.